This thesis is concerned primarily with the architecture of Digital Signal Computers. The work is supported by the design, development and application of a novel Digital Signal Computer system, the MAC68. The MAC68 is a Functional Multiprocessor, using two independent processors, one of which executes general-purpose tasks, and the other executes sequences of arithmetic. The particular MAC68 design was arrived at after careful evaluation of existing Digital Signal Computer architectures. MAC68 features are fully evaluated via its application to the Sub-Band Coding of speech, and in particular by the development of a 16Kb/s Sub-band Coder using six sub-bands. MAC68 performance was found to be comparable to that of current DSP micros for basic digital filter tasks, and superior for FFT tasks. The MAC68 architecture is a balance of high-speed arithmetic and general- purpose capabilities, and is likely to have a greater range of application than General-Purpose micros or DSP micros used alone. Suggestions are put forward for MAC68 enhancements utilising state-of-the-art hardware and software technologies. Because of the current widespread use of General-Purpose micros, and because of the possible performance gains to be had with the MAC68-type architecture, it is thought that MAC68 architectural concepts will be of value in the design of future high-performance Digital Signal Computer systems.
|Date of Award||1985|