Yield model characterization for analog integrated circuit using Pareto-optimal surface

S. Ali; R. Wilcock; P. Wilson; A. Brown

doi:10.1109/ICECS.2008.4675065

Yield model characterization for analog integrated circuit using Pareto-optimal surface

S. Ali, R. Wilcock, P. Wilson, A. Brown

Department of Electronic & Electrical Engineering

Research output: Chapter or section in a book/report/conference proceeding › Chapter in a published conference proceeding

Abstract

A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work.

Original language	English
Title of host publication	15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008
Publisher	IEEE
Pages	1163-1166
ISBN (Print)	9781424421817
DOIs	https://doi.org/10.1109/ICECS.2008.4675065
Publication status	Published - 1 Aug 2008
Event	15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008 - , UK United Kingdom Duration: 31 Aug 2008 → 3 Sep 2008

Conference

Conference	15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008
Country/Territory	UK United Kingdom
Period	31/08/08 → 3/09/08

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10.1109/ICECS.2008.4675065

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Ali, S, Wilcock, R, Wilson, P & Brown, A 2008, Yield model characterization for analog integrated circuit using Pareto-optimal surface. in 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008. IEEE, pp. 1163-1166, 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008 , UK United Kingdom, 31/08/08. https://doi.org/10.1109/ICECS.2008.4675065

@inproceedings{4f9280bef9c4428f8c90379c0dc6ff7e,

title = "Yield model characterization for analog integrated circuit using Pareto-optimal surface",

abstract = "A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work.",

author = "S. Ali and R. Wilcock and P. Wilson and A. Brown",

note = "Event Dates: August 2008; 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008 ; Conference date: 31-08-2008 Through 03-09-2008",

year = "2008",

month = aug,

day = "1",

doi = "10.1109/ICECS.2008.4675065",

language = "English",

isbn = "9781424421817 ",

pages = "1163--1166",

booktitle = "15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008",

publisher = "IEEE",

address = "USA United States",

}

TY - GEN

T1 - Yield model characterization for analog integrated circuit using Pareto-optimal surface

AU - Ali, S.

AU - Wilcock, R.

AU - Wilson, P.

AU - Brown, A.

N1 - Event Dates: August 2008

PY - 2008/8/1

Y1 - 2008/8/1

N2 - A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work.

AB - A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work.

UR - http://dx.doi.org/10.1109/ICECS.2008.4675065

U2 - 10.1109/ICECS.2008.4675065

DO - 10.1109/ICECS.2008.4675065

M3 - Chapter in a published conference proceeding

SN - 9781424421817

SP - 1163

EP - 1166

BT - 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008

PB - IEEE

T2 - 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008

Y2 - 31 August 2008 through 3 September 2008

ER -

Yield model characterization for analog integrated circuit using Pareto-optimal surface

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