A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work.
|Title of host publication||15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008|
|Publication status||Published - 1 Aug 2008|
|Event||15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008 - , UK United Kingdom|
Duration: 31 Aug 2008 → 3 Sep 2008
|Conference||15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008|
|Country||UK United Kingdom|
|Period||31/08/08 → 3/09/08|