Yield model characterization for analog integrated circuit using Pareto-optimal surface

S. Ali, R. Wilcock, P. Wilson, A. Brown

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work.
Original languageEnglish
Title of host publication15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008
PublisherIEEE
Pages1163-1166
ISBN (Print)9781424421817
DOIs
Publication statusPublished - 1 Aug 2008
Event15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008 - , UK United Kingdom
Duration: 31 Aug 20083 Sep 2008

Conference

Conference15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008
CountryUK United Kingdom
Period31/08/083/09/08

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    Ali, S., Wilcock, R., Wilson, P., & Brown, A. (2008). Yield model characterization for analog integrated circuit using Pareto-optimal surface. In 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008 (pp. 1163-1166). IEEE. https://doi.org/10.1109/ICECS.2008.4675065