System-level yield optimisation using hierarchical-based design flow

S. Ali, P. R. Wilson, R. Wilcock

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A new approach in hierarchical optimisation is presented, capable of optimising both the performance and yield of a system-level analogue circuit design. A behavioural model that combines the performance and variation from a Pareto-front is developed which can be used to optimise the system-level structure. The results have been verified with transistor-level simulations of a PLL and suggest that accurate performance and yield prediction can be achieved with the proposed design methodology.

Original languageEnglish
Pages (from-to)605-607
Number of pages3
JournalElectronics Letters
Volume45
Issue number12
DOIs
Publication statusPublished - 19 Jun 2009

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Analog circuits
Phase locked loops
Transistors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

System-level yield optimisation using hierarchical-based design flow. / Ali, S.; Wilson, P. R.; Wilcock, R.

In: Electronics Letters, Vol. 45, No. 12, 19.06.2009, p. 605-607.

Research output: Contribution to journalArticle

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