Si passivation for Ge pMOSFETs

Impact of Si cap growth conditions

B. Vincent, R. Loo, W. Vandervorst, J. Delmotte, B. Douhard, V. K. Valev, M. Vanbel, T. Verbiest, J. Rip, B. Brijs, T. Conard, C. Claypool, S. Takeuchi, S. Zaima, J. Mitard, B. De Jaeger, J. Dekoster, M. Caymax

Research output: Contribution to journalArticle

19 Citations (Scopus)

Abstract

Ultra thin Si cap growth by Reduced Pressure Chemical Vapor Deposition on relaxed Ge substrates is detailed in this paper for Ge pMOSFET (Metal Oxide Semiconductor Field Effect Transistors) passivation purposes. A cross calibration of different measurement techniques is first proposed to perfectly monitor Si monolayers thickness deposited on Ge substrates. Different characteristics, impacting Ge pMOSFETs device performances, are next detailed for various Si cap growth processes using different Si precursors: DiChloroSilane (DCS), silane and trisilane. The critical Si thickness of plastic relaxation has been determined at 12 monolayers. Presence of point defects has been identified for very low growth temperature as 350 °C. Ge-Si intermixing, caused by a Ge segregation mechanism, is strongly reduced by the use of trisilane as Si precursor at low temperatures.

Original languageEnglish
Pages (from-to)116-121
Number of pages6
JournalSolid State Electronics
Volume60
Issue number1
DOIs
Publication statusPublished - 1 Jun 2011

Fingerprint

Passivation
caps
passivity
Monolayers
Silanes
MOSFET devices
Growth temperature
Substrates
Point defects
Chemical vapor deposition
Calibration
Plastics
metal oxide semiconductors
silanes
point defects
plastics
field effect transistors
vapor deposition
Temperature
temperature

Keywords

  • Germanium MOSFET
  • Germanium passivation
  • Low temperature CVD
  • Si precursors
  • Trisilane
  • Ultrathin Si growth on germanium

Cite this

Vincent, B., Loo, R., Vandervorst, W., Delmotte, J., Douhard, B., Valev, V. K., ... Caymax, M. (2011). Si passivation for Ge pMOSFETs: Impact of Si cap growth conditions. Solid State Electronics, 60(1), 116-121. https://doi.org/10.1016/j.sse.2011.01.049

Si passivation for Ge pMOSFETs : Impact of Si cap growth conditions. / Vincent, B.; Loo, R.; Vandervorst, W.; Delmotte, J.; Douhard, B.; Valev, V. K.; Vanbel, M.; Verbiest, T.; Rip, J.; Brijs, B.; Conard, T.; Claypool, C.; Takeuchi, S.; Zaima, S.; Mitard, J.; De Jaeger, B.; Dekoster, J.; Caymax, M.

In: Solid State Electronics, Vol. 60, No. 1, 01.06.2011, p. 116-121.

Research output: Contribution to journalArticle

Vincent, B, Loo, R, Vandervorst, W, Delmotte, J, Douhard, B, Valev, VK, Vanbel, M, Verbiest, T, Rip, J, Brijs, B, Conard, T, Claypool, C, Takeuchi, S, Zaima, S, Mitard, J, De Jaeger, B, Dekoster, J & Caymax, M 2011, 'Si passivation for Ge pMOSFETs: Impact of Si cap growth conditions', Solid State Electronics, vol. 60, no. 1, pp. 116-121. https://doi.org/10.1016/j.sse.2011.01.049
Vincent, B. ; Loo, R. ; Vandervorst, W. ; Delmotte, J. ; Douhard, B. ; Valev, V. K. ; Vanbel, M. ; Verbiest, T. ; Rip, J. ; Brijs, B. ; Conard, T. ; Claypool, C. ; Takeuchi, S. ; Zaima, S. ; Mitard, J. ; De Jaeger, B. ; Dekoster, J. ; Caymax, M. / Si passivation for Ge pMOSFETs : Impact of Si cap growth conditions. In: Solid State Electronics. 2011 ; Vol. 60, No. 1. pp. 116-121.
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