Si passivation for Ge pMOSFETs: Impact of Si cap growth conditions

B. Vincent, R. Loo, W. Vandervorst, J. Delmotte, B. Douhard, V. K. Valev, M. Vanbel, T. Verbiest, J. Rip, B. Brijs, T. Conard, C. Claypool, S. Takeuchi, S. Zaima, J. Mitard, B. De Jaeger, J. Dekoster, M. Caymax

Research output: Contribution to journalArticle

22 Citations (Scopus)

Abstract

Ultra thin Si cap growth by Reduced Pressure Chemical Vapor Deposition on relaxed Ge substrates is detailed in this paper for Ge pMOSFET (Metal Oxide Semiconductor Field Effect Transistors) passivation purposes. A cross calibration of different measurement techniques is first proposed to perfectly monitor Si monolayers thickness deposited on Ge substrates. Different characteristics, impacting Ge pMOSFETs device performances, are next detailed for various Si cap growth processes using different Si precursors: DiChloroSilane (DCS), silane and trisilane. The critical Si thickness of plastic relaxation has been determined at 12 monolayers. Presence of point defects has been identified for very low growth temperature as 350 °C. Ge-Si intermixing, caused by a Ge segregation mechanism, is strongly reduced by the use of trisilane as Si precursor at low temperatures.

Original languageEnglish
Pages (from-to)116-121
Number of pages6
JournalSolid State Electronics
Volume60
Issue number1
DOIs
Publication statusPublished - 1 Jun 2011

Keywords

  • Germanium MOSFET
  • Germanium passivation
  • Low temperature CVD
  • Si precursors
  • Trisilane
  • Ultrathin Si growth on germanium

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