TY - JOUR
T1 - Si passivation for Ge pMOSFETs
T2 - Impact of Si cap growth conditions
AU - Vincent, B.
AU - Loo, R.
AU - Vandervorst, W.
AU - Delmotte, J.
AU - Douhard, B.
AU - Valev, V. K.
AU - Vanbel, M.
AU - Verbiest, T.
AU - Rip, J.
AU - Brijs, B.
AU - Conard, T.
AU - Claypool, C.
AU - Takeuchi, S.
AU - Zaima, S.
AU - Mitard, J.
AU - De Jaeger, B.
AU - Dekoster, J.
AU - Caymax, M.
PY - 2011/6/1
Y1 - 2011/6/1
N2 - Ultra thin Si cap growth by Reduced Pressure Chemical Vapor Deposition on relaxed Ge substrates is detailed in this paper for Ge pMOSFET (Metal Oxide Semiconductor Field Effect Transistors) passivation purposes. A cross calibration of different measurement techniques is first proposed to perfectly monitor Si monolayers thickness deposited on Ge substrates. Different characteristics, impacting Ge pMOSFETs device performances, are next detailed for various Si cap growth processes using different Si precursors: DiChloroSilane (DCS), silane and trisilane. The critical Si thickness of plastic relaxation has been determined at 12 monolayers. Presence of point defects has been identified for very low growth temperature as 350 °C. Ge-Si intermixing, caused by a Ge segregation mechanism, is strongly reduced by the use of trisilane as Si precursor at low temperatures.
AB - Ultra thin Si cap growth by Reduced Pressure Chemical Vapor Deposition on relaxed Ge substrates is detailed in this paper for Ge pMOSFET (Metal Oxide Semiconductor Field Effect Transistors) passivation purposes. A cross calibration of different measurement techniques is first proposed to perfectly monitor Si monolayers thickness deposited on Ge substrates. Different characteristics, impacting Ge pMOSFETs device performances, are next detailed for various Si cap growth processes using different Si precursors: DiChloroSilane (DCS), silane and trisilane. The critical Si thickness of plastic relaxation has been determined at 12 monolayers. Presence of point defects has been identified for very low growth temperature as 350 °C. Ge-Si intermixing, caused by a Ge segregation mechanism, is strongly reduced by the use of trisilane as Si precursor at low temperatures.
KW - Germanium MOSFET
KW - Germanium passivation
KW - Low temperature CVD
KW - Si precursors
KW - Trisilane
KW - Ultrathin Si growth on germanium
UR - http://www.scopus.com/inward/record.url?scp=79955525133&partnerID=8YFLogxK
UR - http://dx.doi.org/10.1016/j.sse.2011.01.049
U2 - 10.1016/j.sse.2011.01.049
DO - 10.1016/j.sse.2011.01.049
M3 - Article
AN - SCOPUS:79955525133
SN - 0038-1101
VL - 60
SP - 116
EP - 121
JO - Solid State Electronics
JF - Solid State Electronics
IS - 1
ER -