Sequence-aware watermark design for soft IP embedded processors

J. Kufel, P. R. Wilson, S. Hill, B. M. Al-Hashimi, P. N. Whatmough

Research output: Contribution to journalArticle

4 Citations (Scopus)
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Abstract

This paper describes a design approach for incorporating sequence-aware watermarks in soft IP embedded processors. The influence of watermark sequence parameters on detection, area and power overheads is examined, and consequently a sequence-aware method for incorporating sequence-aware watermarks in soft IP Embedded Processors is proposed. The intrinsic parameters of sequences, such as the activity factor and the overlapping factor are introduced, and their impact on correlation results is demonstrated. Measurement experimental results from FPGA and ASIC validate the design approach and demonstrate the resulting IP protection and subsequent costs for constrained embedded processors. Results presented in this paper show that the tradeoff occurs between the watermark robustness against third party IP attacks and hardware implementation costs. The analysis of this tradeoff is provided and an application specific watermark implementation is proposed.
Original languageEnglish
Pages (from-to)276-289
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number1
DOIs
Publication statusPublished - 20 Mar 2015

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Application specific integrated circuits
Field programmable gate arrays (FPGA)
Costs
Hardware

Keywords

  • watermarking, IP protection, embedded processors, correlation power analysis

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Sequence-aware watermark design for soft IP embedded processors. / Kufel, J.; Wilson, P. R.; Hill, S.; Al-Hashimi, B. M.; Whatmough, P. N.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 1, 20.03.2015, p. 276-289.

Research output: Contribution to journalArticle

Kufel, J. ; Wilson, P. R. ; Hill, S. ; Al-Hashimi, B. M. ; Whatmough, P. N. / Sequence-aware watermark design for soft IP embedded processors. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2015 ; Vol. 24, No. 1. pp. 276-289.
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