Residue arithmetic techniques for hardware reduction in pseudo-random sequence correlators

C T Clarke; T Srikanthan

Residue arithmetic techniques for hardware reduction in pseudo-random sequence correlators

C T Clarke, T Srikanthan

Department of Electronic & Electrical Engineering

Research output: Contribution to conference › Paper

Abstract

The use of correlators to detect pseudo random number sequences is widespread, and forms the basis of pervasive technologies such as GPS. The correlation function is subject to a trade-off between hardware cost and speed. In this paper we present a residue arithmetic based technique that can create a pseudo random number sequence correlator that has both low hardware cost and high speed.

Original language	English
Pages	1864-1867 Vol.2
Publication status	Published - 2004
Event	38th Asilomar Conference on Signals, Systems and Computers - California, USA United States Duration: 7 Nov 2004 → 10 Nov 2004

Conference

Conference	38th Asilomar Conference on Signals, Systems and Computers
Country/Territory	USA United States
City	California
Period	7/11/04 → 10/11/04

Keywords

hardware reduction
pseudorandom sequence correlators
Global Positioning System
residue number systems
pseudonoise codes
residue arithmetic techniques
random sequences
GPS
correlators

Cite this

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title = "Residue arithmetic techniques for hardware reduction in pseudo-random sequence correlators",

abstract = "The use of correlators to detect pseudo random number sequences is widespread, and forms the basis of pervasive technologies such as GPS. The correlation function is subject to a trade-off between hardware cost and speed. In this paper we present a residue arithmetic based technique that can create a pseudo random number sequence correlator that has both low hardware cost and high speed.",

keywords = "hardware reduction, pseudorandom sequence correlators, Global Positioning System, residue number systems, pseudonoise codes, residue arithmetic techniques, random sequences, GPS, correlators",

author = "Clarke, \{C T\} and T Srikanthan",

year = "2004",

language = "English",

pages = "1864--1867 Vol.2",

note = "38th Asilomar Conference on Signals, Systems and Computers ; Conference date: 07-11-2004 Through 10-11-2004",

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TY - CONF

T1 - Residue arithmetic techniques for hardware reduction in pseudo-random sequence correlators

AU - Clarke, C T

AU - Srikanthan, T

PY - 2004

Y1 - 2004

N2 - The use of correlators to detect pseudo random number sequences is widespread, and forms the basis of pervasive technologies such as GPS. The correlation function is subject to a trade-off between hardware cost and speed. In this paper we present a residue arithmetic based technique that can create a pseudo random number sequence correlator that has both low hardware cost and high speed.

AB - The use of correlators to detect pseudo random number sequences is widespread, and forms the basis of pervasive technologies such as GPS. The correlation function is subject to a trade-off between hardware cost and speed. In this paper we present a residue arithmetic based technique that can create a pseudo random number sequence correlator that has both low hardware cost and high speed.

KW - hardware reduction

KW - pseudorandom sequence correlators

KW - Global Positioning System

KW - residue number systems

KW - pseudonoise codes

KW - residue arithmetic techniques

KW - random sequences

KW - GPS

KW - correlators

UR - https://www.scopus.com/pages/publications/21644474596

M3 - Paper

SP - 1864-1867 Vol.2

T2 - 38th Asilomar Conference on Signals, Systems and Computers

Y2 - 7 November 2004 through 10 November 2004

ER -

Residue arithmetic techniques for hardware reduction in pseudo-random sequence correlators

Abstract

Conference

Keywords

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