Residue arithmetic techniques for hardware reduction in pseudo-random sequence correlators

C T Clarke, T Srikanthan

Research output: Contribution to conferencePaper

Abstract

The use of correlators to detect pseudo random number sequences is widespread, and forms the basis of pervasive technologies such as GPS. The correlation function is subject to a trade-off between hardware cost and speed. In this paper we present a residue arithmetic based technique that can create a pseudo random number sequence correlator that has both low hardware cost and high speed.
Original languageEnglish
Pages1864-1867 Vol.2
Publication statusPublished - 2004
Event38th Asilomar Conference on Signals, Systems and Computers - California, USA United States
Duration: 7 Nov 200410 Nov 2004

Conference

Conference38th Asilomar Conference on Signals, Systems and Computers
CountryUSA United States
CityCalifornia
Period7/11/0410/11/04

Keywords

  • hardware reduction
  • pseudorandom sequence correlators
  • Global Positioning System
  • residue number systems
  • pseudonoise codes
  • residue arithmetic techniques
  • random sequences
  • GPS
  • correlators

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  • Cite this

    Clarke, C. T., & Srikanthan, T. (2004). Residue arithmetic techniques for hardware reduction in pseudo-random sequence correlators. 1864-1867 Vol.2. Paper presented at 38th Asilomar Conference on Signals, Systems and Computers, California, USA United States.