The use of correlators to detect pseudo random number sequences is widespread, and forms the basis of pervasive technologies such as GPS. The correlation function is subject to a trade-off between hardware cost and speed. In this paper we present a residue arithmetic based technique that can create a pseudo random number sequence correlator that has both low hardware cost and high speed.
|Publication status||Published - 2004|
|Event||38th Asilomar Conference on Signals, Systems and Computers - California, USA United States|
Duration: 7 Nov 2004 → 10 Nov 2004
|Conference||38th Asilomar Conference on Signals, Systems and Computers|
|Country||USA United States|
|Period||7/11/04 → 10/11/04|
- hardware reduction
- pseudorandom sequence correlators
- Global Positioning System
- residue number systems
- pseudonoise codes
- residue arithmetic techniques
- random sequences
Clarke, C. T., & Srikanthan, T. (2004). Residue arithmetic techniques for hardware reduction in pseudo-random sequence correlators. 1864-1867 Vol.2. Paper presented at 38th Asilomar Conference on Signals, Systems and Computers, California, USA United States.