Rapid evaluation of custom instruction selection approaches with FPGA estimation

Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke

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Abstract

The main aim of this article is to demonstrate that a fast and accurate FPGA estimation engine is indispensable in design flows for custom instruction (template) selection. The need for a FPGA estimation engine stems from the difficulty in predicting the FPGA performance measures of selected custom instructions. We will present a FPGA estimation technique that partitions the high-level representation of custom instructions into clusters based on the structural organization of the target FPGA, while taking into account general logic synthesis principles adopted by FPGA tools. In this work, we have evaluated a widely used graph covering algorithm with various heuristics for custom instruction selection. In addition, we present an algorithm called Refined Largest Fit First (RLFF) that relies on a graph covering heuristic to select nonoverlapping superset templates, which typically incorporate frequently used basic templates. The initial solution is further refined by considering overlapping templates that were ignored previously to see if their introduction could lead to higher performance. While RLFF provides the most efficient cover compared to the ILP method and other graph covering heuristics, FPGA estimation results reveals that RLFF leads to the worst performance in certain applications. It is therefore a worthy proposition to equip design flows with accurate FPGA estimation in order to rapidly determine the most profitable custom instruction approach for a given application.

Original languageEnglish
Article number75
Pages (from-to)1 - 29
Number of pages29
JournalACM Transactions on Embedded Computing Systems
Volume13
Issue number4
DOIs
Publication statusPublished - Nov 2014

Keywords

  • Approximation algorithms
  • Customizable processors
  • FPGA
  • ISA extension

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