Rail to rail CMOS complementary input stage with only one active differential pair at a time

Maria Rodanas Valero; Alejandro Roman-Loera; Jaime Ramírez-Angulo; Nicolas Medrano; Santiago Celma

doi:10.1587/elex.11.20140392

Rail to rail CMOS complementary input stage with only one active differential pair at a time

Maria Rodanas Valero, Alejandro Roman-Loera, Jaime Ramírez-Angulo, Nicolas Medrano, Santiago Celma

Department of Electronic & Electrical Engineering

Research output: Contribution to journal › Letter › peer-review

2 Citations (SciVal)

Abstract

A simple scheme for rail to rail op-amp operation is introduced. The input stage uses complementary differential pairs but only one pair is active at a time. It uses very compact control circuitry. Experimental verification is provided from a test chip prototype in 0.5μm CMOS technology.

Original language	English
Journal	IEICE Electronics Express
Volume	11
Issue number	12
DOIs	https://doi.org/10.1587/elex.11.20140392
Publication status	Published - 1 Jan 2014

Keywords

Amplifiers
Analog integrated circuits
CMOS integrated circuits
Low-voltage low power design

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

Access to Document

10.1587/elex.11.20140392

Cite this

@article{1674980f19d84876a3169c715dff6c0c,

title = "Rail to rail CMOS complementary input stage with only one active differential pair at a time",

abstract = "A simple scheme for rail to rail op-amp operation is introduced. The input stage uses complementary differential pairs but only one pair is active at a time. It uses very compact control circuitry. Experimental verification is provided from a test chip prototype in 0.5μm CMOS technology.",

keywords = "Amplifiers, Analog integrated circuits, CMOS integrated circuits, Low-voltage low power design",

author = "Valero, {Maria Rodanas} and Alejandro Roman-Loera and Jaime Ram{\'i}rez-Angulo and Nicolas Medrano and Santiago Celma",

year = "2014",

month = jan,

day = "1",

doi = "10.1587/elex.11.20140392",

language = "English",

volume = "11",

journal = "IEICE Electronics Express",

issn = "1349-2543",

publisher = "Institute of Electronics Information and Communication Engineers (IEICE)",

number = "12",

}

TY - JOUR

T1 - Rail to rail CMOS complementary input stage with only one active differential pair at a time

AU - Valero, Maria Rodanas

AU - Roman-Loera, Alejandro

AU - Ramírez-Angulo, Jaime

AU - Medrano, Nicolas

AU - Celma, Santiago

PY - 2014/1/1

Y1 - 2014/1/1

N2 - A simple scheme for rail to rail op-amp operation is introduced. The input stage uses complementary differential pairs but only one pair is active at a time. It uses very compact control circuitry. Experimental verification is provided from a test chip prototype in 0.5μm CMOS technology.

AB - A simple scheme for rail to rail op-amp operation is introduced. The input stage uses complementary differential pairs but only one pair is active at a time. It uses very compact control circuitry. Experimental verification is provided from a test chip prototype in 0.5μm CMOS technology.

KW - Amplifiers

KW - Analog integrated circuits

KW - CMOS integrated circuits

KW - Low-voltage low power design

UR - http://www.scopus.com/inward/record.url?scp=84903135412&partnerID=8YFLogxK

U2 - 10.1587/elex.11.20140392

DO - 10.1587/elex.11.20140392

M3 - Letter

AN - SCOPUS:84903135412

SN - 1349-2543

VL - 11

JO - IEICE Electronics Express

JF - IEICE Electronics Express

IS - 12

ER -

Rail to rail CMOS complementary input stage with only one active differential pair at a time

Abstract

Keywords

ASJC Scopus subject areas

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