@conference{cf91e8072acd438cae415a3643fe6f31,
title = "PSRR enhancement based on QFG techniques for low-voltage low-power design: 2014 IEEE International Symposium on Circuits and Systems (ISCAS)",
keywords = "MOSFET, analogue integrated circuits, low-power electronics, AC noise, LVLP DC circuits, PSRR enhancement technique, QFG techniques, biasing circuits, low voltage power low power DC circuits, power supply rejection ratio enhancement technique, supply rails, total internal noise, Educational institutions, Integrated circuit modeling, Logic gates, Noise, Rails, Semiconductor device modeling, Transistors, Analog integrated circuits, CMOS integrated circuits, low-voltage low power design",
author = "Valero, {M. R.} and J. Ram{\'i}rez-Angulo and N. Medrano and S. Celma",
year = "2014",
doi = "10.1109/ISCAS.2014.6865726",
language = "English",
pages = "2684--2687",
}