PSRR enhancement based on QFG techniques for low-voltage low-power design: 2014 IEEE International Symposium on Circuits and Systems (ISCAS)

M. R. Valero, J. Ramírez-Angulo, N. Medrano, S. Celma

Research output: Contribution to conferencePaper

Original languageEnglish
Pages2684-2687
Number of pages4
DOIs
Publication statusPublished - 2014

Keywords

  • MOSFET
  • analogue integrated circuits
  • low-power electronics
  • AC noise
  • LVLP DC circuits
  • PSRR enhancement technique
  • QFG techniques
  • biasing circuits
  • low voltage power low power DC circuits
  • power supply rejection ratio enhancement technique
  • supply rails
  • total internal noise
  • Educational institutions
  • Integrated circuit modeling
  • Logic gates
  • Noise
  • Rails
  • Semiconductor device modeling
  • Transistors
  • Analog integrated circuits
  • CMOS integrated circuits
  • low-voltage low power design

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