PSRR enhancement based on QFG techniques for low-voltage low-power design

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

M. R. Valero, J. Ramírez-Angulo, N. Medrano, S. Celma

Research output: Contribution to conferencePaper

Original languageEnglish
Pages2684-2687
Number of pages4
DOIs
Publication statusPublished - 2014

Keywords

  • MOSFET
  • analogue integrated circuits
  • low-power electronics
  • AC noise
  • LVLP DC circuits
  • PSRR enhancement technique
  • QFG techniques
  • biasing circuits
  • low voltage power low power DC circuits
  • power supply rejection ratio enhancement technique
  • supply rails
  • total internal noise
  • Educational institutions
  • Integrated circuit modeling
  • Logic gates
  • Noise
  • Rails
  • Semiconductor device modeling
  • Transistors
  • Analog integrated circuits
  • CMOS integrated circuits
  • low-voltage low power design

Cite this

PSRR enhancement based on QFG techniques for low-voltage low-power design : 2014 IEEE International Symposium on Circuits and Systems (ISCAS). / Valero, M. R.; Ramírez-Angulo, J.; Medrano, N.; Celma, S.

2014. 2684-2687.

Research output: Contribution to conferencePaper

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title = "PSRR enhancement based on QFG techniques for low-voltage low-power design: 2014 IEEE International Symposium on Circuits and Systems (ISCAS)",
keywords = "MOSFET, analogue integrated circuits, low-power electronics, AC noise, LVLP DC circuits, PSRR enhancement technique, QFG techniques, biasing circuits, low voltage power low power DC circuits, power supply rejection ratio enhancement technique, supply rails, total internal noise, Educational institutions, Integrated circuit modeling, Logic gates, Noise, Rails, Semiconductor device modeling, Transistors, Analog integrated circuits, CMOS integrated circuits, low-voltage low power design",
author = "Valero, {M. R.} and J. Ram{\'i}rez-Angulo and N. Medrano and S. Celma",
year = "2014",
doi = "10.1109/ISCAS.2014.6865726",
language = "English",
pages = "2684--2687",

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T1 - PSRR enhancement based on QFG techniques for low-voltage low-power design

T2 - 2014 IEEE International Symposium on Circuits and Systems (ISCAS)

AU - Valero, M. R.

AU - Ramírez-Angulo, J.

AU - Medrano, N.

AU - Celma, S.

PY - 2014

Y1 - 2014

KW - MOSFET

KW - analogue integrated circuits

KW - low-power electronics

KW - AC noise

KW - LVLP DC circuits

KW - PSRR enhancement technique

KW - QFG techniques

KW - biasing circuits

KW - low voltage power low power DC circuits

KW - power supply rejection ratio enhancement technique

KW - supply rails

KW - total internal noise

KW - Educational institutions

KW - Integrated circuit modeling

KW - Logic gates

KW - Noise

KW - Rails

KW - Semiconductor device modeling

KW - Transistors

KW - Analog integrated circuits

KW - CMOS integrated circuits

KW - low-voltage low power design

U2 - 10.1109/ISCAS.2014.6865726

DO - 10.1109/ISCAS.2014.6865726

M3 - Paper

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EP - 2687

ER -