Cache memories improve the performance due to the locality found within the loops of application. Because these loop characteristics are application dependent, the optimal cache hierarchy for performance and energy saving is also application dependent. Traditionally, cache simulations are employed to tune the cache hierarchy. In this paper we propose a simple yet effective loop profiler directed methodology for instruction cache hierarchy optimization. The proposed methodology utilizes the loop characteristics of the application which are readily available from the compiler making it easy to adopt the methodology in an existing design flow.
|Publication status||Published - 2 Mar 2006|
|Event||IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures - Karlsruhe, Germany|
Duration: 2 Mar 2006 → 3 Mar 2006
|Conference||IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures|
|Period||2/03/06 → 3/03/06|