Profile directed instruction cache tuning for embedded systems

K Vivekanandarajah, T Srikanthan, C T Clarke

Research output: Contribution to conferencePaper

6 Citations (Scopus)

Abstract

Cache memories improve the performance due to the locality found within the loops of application. Because these loop characteristics are application dependent, the optimal cache hierarchy for performance and energy saving is also application dependent. Traditionally, cache simulations are employed to tune the cache hierarchy. In this paper we propose a simple yet effective loop profiler directed methodology for instruction cache hierarchy optimization. The proposed methodology utilizes the loop characteristics of the application which are readily available from the compiler making it easy to adopt the methodology in an existing design flow.
Original languageEnglish
DOIs
Publication statusPublished - 2 Mar 2006
EventIEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures - Karlsruhe, Germany
Duration: 2 Mar 20063 Mar 2006

Conference

ConferenceIEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
CountryGermany
CityKarlsruhe
Period2/03/063/03/06

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    Vivekanandarajah, K., Srikanthan, T., & Clarke, C. T. (2006). Profile directed instruction cache tuning for embedded systems. Paper presented at IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, Karlsruhe, Germany. https://doi.org/10.1109/ISVLSI.2006.75