Profile directed instruction cache tuning for embedded systems

K Vivekanandarajah; T Srikanthan; C T Clarke

doi:10.1109/ISVLSI.2006.75

Profile directed instruction cache tuning for embedded systems

K Vivekanandarajah, T Srikanthan, C T Clarke

Department of Electronic & Electrical Engineering

Research output: Contribution to conference › Paper

6 Citations (SciVal)

Abstract

Cache memories improve the performance due to the locality found within the loops of application. Because these loop characteristics are application dependent, the optimal cache hierarchy for performance and energy saving is also application dependent. Traditionally, cache simulations are employed to tune the cache hierarchy. In this paper we propose a simple yet effective loop profiler directed methodology for instruction cache hierarchy optimization. The proposed methodology utilizes the loop characteristics of the application which are readily available from the compiler making it easy to adopt the methodology in an existing design flow.

Original language	English
DOIs	https://doi.org/10.1109/ISVLSI.2006.75
Publication status	Published - 2 Mar 2006
Event	IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures - Karlsruhe, Germany Duration: 2 Mar 2006 → 3 Mar 2006

Conference

Conference	IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Country/Territory	Germany
City	Karlsruhe
Period	2/03/06 → 3/03/06

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10.1109/ISVLSI.2006.75

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title = "Profile directed instruction cache tuning for embedded systems",

abstract = "Cache memories improve the performance due to the locality found within the loops of application. Because these loop characteristics are application dependent, the optimal cache hierarchy for performance and energy saving is also application dependent. Traditionally, cache simulations are employed to tune the cache hierarchy. In this paper we propose a simple yet effective loop profiler directed methodology for instruction cache hierarchy optimization. The proposed methodology utilizes the loop characteristics of the application which are readily available from the compiler making it easy to adopt the methodology in an existing design flow.",

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year = "2006",

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AU - Vivekanandarajah, K

AU - Srikanthan, T

AU - Clarke, C T

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N2 - Cache memories improve the performance due to the locality found within the loops of application. Because these loop characteristics are application dependent, the optimal cache hierarchy for performance and energy saving is also application dependent. Traditionally, cache simulations are employed to tune the cache hierarchy. In this paper we propose a simple yet effective loop profiler directed methodology for instruction cache hierarchy optimization. The proposed methodology utilizes the loop characteristics of the application which are readily available from the compiler making it easy to adopt the methodology in an existing design flow.

AB - Cache memories improve the performance due to the locality found within the loops of application. Because these loop characteristics are application dependent, the optimal cache hierarchy for performance and energy saving is also application dependent. Traditionally, cache simulations are employed to tune the cache hierarchy. In this paper we propose a simple yet effective loop profiler directed methodology for instruction cache hierarchy optimization. The proposed methodology utilizes the loop characteristics of the application which are readily available from the compiler making it easy to adopt the methodology in an existing design flow.

UR - http://dx.doi.org/10.1109/ISVLSI.2006.75

U2 - 10.1109/ISVLSI.2006.75

DO - 10.1109/ISVLSI.2006.75

M3 - Paper

T2 - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures

Y2 - 2 March 2006 through 3 March 2006

ER -

Profile directed instruction cache tuning for embedded systems

Abstract

Conference

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