Power aware learning for class AB analogue VLSI neural network

Sankalp Modi; Peter Wilson; Andrew Brown

doi:10.1109/ISCAS.2006.1692814

Power aware learning for class AB analogue VLSI neural network

Sankalp Modi, Peter Wilson, Andrew Brown

Department of Electronic & Electrical Engineering

Research output: Chapter or section in a book/report/conference proceeding › Chapter in a published conference proceeding

Abstract

Recent research into Artificial Neural Networks (ANN) has highlighted the potential of using compact analogue ANN hardware cores in embedded mobile devices, where power consumption of ANN hardware is a very significant implementation issue. This paper proposes a learning mechanism suitable for low-power class AB type analogue ANN that not only tunes the network to obtain minimum error, but also adaptively learns to reduce power consumption. Our experiments show substantial reductions in the power budget (30% to 50 for a variety of example networks as a result of our power-aware learning.

Original language	English
Title of host publication	Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2006
Publisher	IEEE
ISBN (Print)	0780393899
DOIs	https://doi.org/10.1109/ISCAS.2006.1692814
Publication status	Published - 2006
Event	IEEE International Symposium on Circuits and Systems (ISCAS), 2006 - Island of Kos, Greece Duration: 21 May 2006 → 24 May 2006

Conference

Conference	IEEE International Symposium on Circuits and Systems (ISCAS), 2006
Country/Territory	Greece
Period	21/05/06 → 24/05/06

Keywords

Artificial Neural Networks, ANN hardware, Low-power, Power-aware, learning

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10.1109/ISCAS.2006.1692814

Cite this

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title = "Power aware learning for class AB analogue VLSI neural network",

abstract = "Recent research into Artificial Neural Networks (ANN) has highlighted the potential of using compact analogue ANN hardware cores in embedded mobile devices, where power consumption of ANN hardware is a very significant implementation issue. This paper proposes a learning mechanism suitable for low-power class AB type analogue ANN that not only tunes the network to obtain minimum error, but also adaptively learns to reduce power consumption. Our experiments show substantial reductions in the power budget (30% to 50 for a variety of example networks as a result of our power-aware learning.",

keywords = "Artificial Neural Networks, ANN hardware, Low-power, Power-aware, learning",

author = "Sankalp Modi and Peter Wilson and Andrew Brown",

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language = "English",

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booktitle = "Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2006",

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note = "IEEE International Symposium on Circuits and Systems (ISCAS), 2006 ; Conference date: 21-05-2006 Through 24-05-2006",

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T1 - Power aware learning for class AB analogue VLSI neural network

AU - Modi, Sankalp

AU - Wilson, Peter

AU - Brown, Andrew

PY - 2006

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N2 - Recent research into Artificial Neural Networks (ANN) has highlighted the potential of using compact analogue ANN hardware cores in embedded mobile devices, where power consumption of ANN hardware is a very significant implementation issue. This paper proposes a learning mechanism suitable for low-power class AB type analogue ANN that not only tunes the network to obtain minimum error, but also adaptively learns to reduce power consumption. Our experiments show substantial reductions in the power budget (30% to 50 for a variety of example networks as a result of our power-aware learning.

AB - Recent research into Artificial Neural Networks (ANN) has highlighted the potential of using compact analogue ANN hardware cores in embedded mobile devices, where power consumption of ANN hardware is a very significant implementation issue. This paper proposes a learning mechanism suitable for low-power class AB type analogue ANN that not only tunes the network to obtain minimum error, but also adaptively learns to reduce power consumption. Our experiments show substantial reductions in the power budget (30% to 50 for a variety of example networks as a result of our power-aware learning.

KW - Artificial Neural Networks, ANN hardware, Low-power, Power-aware, learning

UR - http://dx.doi.org/10.1109/ISCAS.2006.1692814

U2 - 10.1109/ISCAS.2006.1692814

DO - 10.1109/ISCAS.2006.1692814

M3 - Chapter in a published conference proceeding

SN - 0780393899

BT - Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2006

PB - IEEE

T2 - IEEE International Symposium on Circuits and Systems (ISCAS), 2006

Y2 - 21 May 2006 through 24 May 2006

ER -

Power aware learning for class AB analogue VLSI neural network

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