Power aware learning for class AB analogue VLSI neural network

Sankalp Modi, Peter Wilson, Andrew Brown

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recent research into Artificial Neural Networks (ANN) has highlighted the potential of using compact analogue ANN hardware cores in embedded mobile devices, where power consumption of ANN hardware is a very significant implementation issue. This paper proposes a learning mechanism suitable for low-power class AB type analogue ANN that not only tunes the network to obtain minimum error, but also adaptively learns to reduce power consumption. Our experiments show substantial reductions in the power budget (30% to 50 for a variety of example networks as a result of our power-aware learning.
Original languageEnglish
Title of host publicationProceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2006
PublisherIEEE
ISBN (Print)0780393899
DOIs
Publication statusPublished - 2006
EventIEEE International Symposium on Circuits and Systems (ISCAS), 2006 - Island of Kos, Greece
Duration: 21 May 200624 May 2006

Conference

ConferenceIEEE International Symposium on Circuits and Systems (ISCAS), 2006
CountryGreece
Period21/05/0624/05/06

Keywords

  • Artificial Neural Networks, ANN hardware, Low-power, Power-aware, learning

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  • Cite this

    Modi, S., Wilson, P., & Brown, A. (2006). Power aware learning for class AB analogue VLSI neural network. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2006 IEEE. https://doi.org/10.1109/ISCAS.2006.1692814