Recent research into Artificial Neural Networks (ANN) has highlighted the potential of using compact analogue ANN hardware cores in embedded mobile devices, where power consumption of ANN hardware is a very significant implementation issue. This paper proposes a learning mechanism suitable for low-power class AB type analogue ANN that not only tunes the network to obtain minimum error, but also adaptively learns to reduce power consumption. Our experiments show substantial reductions in the power budget (30% to 50 for a variety of example networks as a result of our power-aware learning.
|Title of host publication||Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2006|
|Publication status||Published - 2006|
|Event||IEEE International Symposium on Circuits and Systems (ISCAS), 2006 - Island of Kos, Greece|
Duration: 21 May 2006 → 24 May 2006
|Conference||IEEE International Symposium on Circuits and Systems (ISCAS), 2006|
|Period||21/05/06 → 24/05/06|
- Artificial Neural Networks, ANN hardware, Low-power, Power-aware, learning