Performance of thin-film transistors fabricated by sequential lateral solidification crystallization techniques

The performance of Excimer Laser Annealed (ELA) Thin-Film Transistors (TFTs), in terms of drain current behaviour in unstressed as well as in DC stressed devices, is presented. The transistors studied were fabricated under different irradiation schemes of a novel Sequential Lateral Solidification (SLS) process. As fer as unstressed transistors concerned, drain current transients relaxed through stretched exponential law. Fitting results disclosed that both gate dielectric polarization and carrier recombination mechanisms occurred through transient relaxation. Deep Level Transient Spectroscopy (DLTS) technique was called forth in order to investigate the origin of carrier recombination mechanisms. DC hot carrier stress measurements, under "worst ageing condition" regime, were conducted in order to probe degradation mechanisms and device reliability standards. Crystal domain size significantly affects threshold voltage degradation. The latter increases with decreasing crystal domain size, due to increased concentration of protrusions in the polysilicon film. Transconductance degradation also depends on crystal domain size, attributed mainly to bulk polysilicon trap generation.