Optimal sizing of configurable devices to reduce variability in integrated circuits

P. Wilson, R. Wilcock

Research output: Chapter in Book/Report/Conference proceedingChapter

3 Citations (Scopus)

Abstract

This paper describes a systematic approach that facilitates yield improvement of integrated circuits at the post-manufacture stage. A new Configurable Analogue Transistor (CAT) structure is presented that allows the adjustment of devices after manufacture. The technique enables both performance and yield to be improved as part of the normal test process. The optimal sizing of the inserted CAT devices is crucial to ensure the greatest improvement in yield and this paper considers this challenge in detail. An analysis and description of the underlying theory of the sizing problem is given along with examples of incorrect sizing. Guidelines to achieve optimal CAT sizing are proposed, and results are provided to demonstrate the overall effectiveness of the CAT approach.
Original languageEnglish
Title of host publicationDesign, Automation & Test in Europe Conference & Exhibition (DATE) 2009
PublisherIEEE
Pages1385-1390
ISBN (Print)9781424437818
DOIs
Publication statusPublished - 1 Apr 2009
EventDesign, Automation & Test in Europe Conference & Exhibition (DATE), 2009 - Nice, France
Duration: 20 Apr 200924 Apr 2009

Conference

ConferenceDesign, Automation & Test in Europe Conference & Exhibition (DATE), 2009
CountryFrance
CityNice
Period20/04/0924/04/09

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