On the study of p-channel thin-film transistors fabricated by SLS ELA crystallization techniques

M. A. Exarchos; D. C. Moschou; G. J. Papaioannou; D. N. Kouvatsos; A. Arapoyanni; A. T. Voutsas

doi:10.1016/j.tsf.2009.02.052

On the study of p-channel thin-film transistors fabricated by SLS ELA crystallization techniques

M. A. Exarchos, D. C. Moschou, G. J. Papaioannou, D. N. Kouvatsos, A. Arapoyanni, A. T. Voutsas

Department of Electronic & Electrical Engineering

Research output: Contribution to journal › Article › peer-review

8 Citations (SciVal)

Abstract

The electrical characterization, in terms of drain current, of SLS ELA p-channel polysilicon TFTs is investigated. The study was based on the DLTS technique. It was found that drain current is governed by trapping/detrapping mechanisms associated to poly-Si/SiO ₂ interface states. This fact is in accordance with the results of stretched exponential analysis applied on switch-ON drain current transients. DC hot carrier measurements under worse ageing condition regime were also conducted. Threshold voltage and transconductance variation revealed that hole injection towards the gate oxide is the prevailing mechanism, while poly-Si/SiO ₂ interface degradation seems to be minor.

Original language	English
Pages (from-to)	6375-6378
Number of pages	4
Journal	Thin Solid Films
Volume	517
Issue number	23
DOIs	https://doi.org/10.1016/j.tsf.2009.02.052
Publication status	Published - 1 Oct 2009

Keywords

DLTS
p-TFT reliability
Poly-Si TFTs
SLS ELA crystallization

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Materials Chemistry
Metals and Alloys
Surfaces, Coatings and Films
Surfaces and Interfaces

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10.1016/j.tsf.2009.02.052

https://doi.org/10.1016/j.tsf.2009.02.052

Cite this

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title = "On the study of p-channel thin-film transistors fabricated by SLS ELA crystallization techniques",

abstract = "The electrical characterization, in terms of drain current, of SLS ELA p-channel polysilicon TFTs is investigated. The study was based on the DLTS technique. It was found that drain current is governed by trapping/detrapping mechanisms associated to poly-Si/SiO 2 interface states. This fact is in accordance with the results of stretched exponential analysis applied on switch-ON drain current transients. DC hot carrier measurements under worse ageing condition regime were also conducted. Threshold voltage and transconductance variation revealed that hole injection towards the gate oxide is the prevailing mechanism, while poly-Si/SiO 2 interface degradation seems to be minor.",

keywords = "DLTS, p-TFT reliability, Poly-Si TFTs, SLS ELA crystallization",

author = "Exarchos, {M. A.} and Moschou, {D. C.} and Papaioannou, {G. J.} and Kouvatsos, {D. N.} and A. Arapoyanni and Voutsas, {A. T.}",

year = "2009",

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doi = "10.1016/j.tsf.2009.02.052",

language = "English",

volume = "517",

pages = "6375--6378",

journal = "Thin Solid Films",

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TY - JOUR

T1 - On the study of p-channel thin-film transistors fabricated by SLS ELA crystallization techniques

AU - Exarchos, M. A.

AU - Moschou, D. C.

AU - Papaioannou, G. J.

AU - Kouvatsos, D. N.

AU - Arapoyanni, A.

AU - Voutsas, A. T.

PY - 2009/10/1

Y1 - 2009/10/1

N2 - The electrical characterization, in terms of drain current, of SLS ELA p-channel polysilicon TFTs is investigated. The study was based on the DLTS technique. It was found that drain current is governed by trapping/detrapping mechanisms associated to poly-Si/SiO 2 interface states. This fact is in accordance with the results of stretched exponential analysis applied on switch-ON drain current transients. DC hot carrier measurements under worse ageing condition regime were also conducted. Threshold voltage and transconductance variation revealed that hole injection towards the gate oxide is the prevailing mechanism, while poly-Si/SiO 2 interface degradation seems to be minor.

AB - The electrical characterization, in terms of drain current, of SLS ELA p-channel polysilicon TFTs is investigated. The study was based on the DLTS technique. It was found that drain current is governed by trapping/detrapping mechanisms associated to poly-Si/SiO 2 interface states. This fact is in accordance with the results of stretched exponential analysis applied on switch-ON drain current transients. DC hot carrier measurements under worse ageing condition regime were also conducted. Threshold voltage and transconductance variation revealed that hole injection towards the gate oxide is the prevailing mechanism, while poly-Si/SiO 2 interface degradation seems to be minor.

KW - DLTS

KW - p-TFT reliability

KW - Poly-Si TFTs

KW - SLS ELA crystallization

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UR - https://doi.org/10.1016/j.tsf.2009.02.052

U2 - 10.1016/j.tsf.2009.02.052

DO - 10.1016/j.tsf.2009.02.052

M3 - Article

AN - SCOPUS:68449101312

SN - 0040-6090

VL - 517

SP - 6375

EP - 6378

JO - Thin Solid Films

JF - Thin Solid Films

IS - 23

ER -

On the study of p-channel thin-film transistors fabricated by SLS ELA crystallization techniques

Abstract

Keywords

ASJC Scopus subject areas

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