Abstract
A new timing measurement architecture based on the time-to-digital conversion technique is presented. The architecture occupies a small silicon area (200x185um) in a 0.12um CMOS Process and can achieve tens of femtoseconds timing resolution, which is the highest reported to date.
| Original language | Undefined/Unknown |
|---|---|
| Pages (from-to) | 528-530 |
| Number of pages | 3 |
| Journal | Electronics Letters |
| Volume | 42 |
| Issue number | 9 |
| Publication status | Published - 1 Apr 2006 |
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