On-chip timing measurement architecture with femtosecond resolution

Matthew Collins, Bashir Al-Hashimi, Peter Wilson

Research output: Contribution to journalArticlepeer-review

6 Citations (SciVal)


A new timing measurement architecture based on the time-to-digital conversion technique is presented. The architecture occupies a small silicon area (200x185um) in a 0.12um CMOS Process and can achieve tens of femtoseconds timing resolution, which is the highest reported to date.
Original languageUndefined/Unknown
Pages (from-to)528-530
Number of pages3
JournalElectronics Letters
Issue number9
Publication statusPublished - 1 Apr 2006

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