On-chip timing measurement architecture with femtosecond resolution

Matthew Collins; Bashir Al-Hashimi; Peter Wilson

On-chip timing measurement architecture with femtosecond resolution

Matthew Collins, Bashir Al-Hashimi, Peter Wilson

Department of Electronic & Electrical Engineering

Research output: Contribution to journal › Article › peer-review

6 Citations (SciVal)

Abstract

A new timing measurement architecture based on the time-to-digital conversion technique is presented. The architecture occupies a small silicon area (200x185um) in a 0.12um CMOS Process and can achieve tens of femtoseconds timing resolution, which is the highest reported to date.

Original language	Undefined/Unknown
Pages (from-to)	528-530
Number of pages	3
Journal	Electronics Letters
Volume	42
Issue number	9
Publication status	Published - 1 Apr 2006

Cite this

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title = "On-chip timing measurement architecture with femtosecond resolution",

abstract = "A new timing measurement architecture based on the time-to-digital conversion technique is presented. The architecture occupies a small silicon area (200x185um) in a 0.12um CMOS Process and can achieve tens of femtoseconds timing resolution, which is the highest reported to date.",

author = "Matthew Collins and Bashir Al-Hashimi and Peter Wilson",

year = "2006",

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T1 - On-chip timing measurement architecture with femtosecond resolution

AU - Collins, Matthew

AU - Al-Hashimi, Bashir

AU - Wilson, Peter

PY - 2006/4/1

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N2 - A new timing measurement architecture based on the time-to-digital conversion technique is presented. The architecture occupies a small silicon area (200x185um) in a 0.12um CMOS Process and can achieve tens of femtoseconds timing resolution, which is the highest reported to date.

AB - A new timing measurement architecture based on the time-to-digital conversion technique is presented. The architecture occupies a small silicon area (200x185um) in a 0.12um CMOS Process and can achieve tens of femtoseconds timing resolution, which is the highest reported to date.

UR - http://eprints.soton.ac.uk/262543/

M3 - Article

SN - 0013-5194

VL - 42

SP - 528

EP - 530

JO - Electronics Letters

JF - Electronics Letters

IS - 9

ER -

On-chip timing measurement architecture with femtosecond resolution

Abstract

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