On-chip timing measurement architecture with femtosecond resolution

Matthew Collins, Bashir Al-Hashimi, Peter Wilson

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

A new timing measurement architecture based on the time-to-digital conversion technique is presented. The architecture occupies a small silicon area (200x185um) in a 0.12um CMOS Process and can achieve tens of femtoseconds timing resolution, which is the highest reported to date.
Original languageUndefined/Unknown
Pages (from-to)528-530
Number of pages3
JournalElectronics Letters
Volume42
Issue number9
Publication statusPublished - 1 Apr 2006

Cite this

On-chip timing measurement architecture with femtosecond resolution. / Collins, Matthew; Al-Hashimi, Bashir; Wilson, Peter.

In: Electronics Letters, Vol. 42, No. 9, 01.04.2006, p. 528-530.

Research output: Contribution to journalArticle

Collins, M, Al-Hashimi, B & Wilson, P 2006, 'On-chip timing measurement architecture with femtosecond resolution', Electronics Letters, vol. 42, no. 9, pp. 528-530.
Collins, Matthew ; Al-Hashimi, Bashir ; Wilson, Peter. / On-chip timing measurement architecture with femtosecond resolution. In: Electronics Letters. 2006 ; Vol. 42, No. 9. pp. 528-530.
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