Low latency optical switch for high performance computing with minimized processor energy load [Invited]

Shiyun Liu, Qixiang Cheng, Muhammad Ridwan Madarbux, Adrian Wonfor, Richard V. Penty, Ian H. White, Philip M. Watts

Research output: Contribution to journalArticle

13 Citations (Scopus)

Abstract

Power density and cooling issues are limiting the performance of high performance chip multiprocessors (CMPs), and off-chip communications currently consume more than 20% of power for memory, coherence, PCI, and Ethernet links. Photonic transceivers integrated with CMPs are being developed to overcome these issues, potentially allowing low hop count switched connections between chips or data center servers. However, latency in setting up optical connections is critically important in all computing applications, and having transceivers integrated on the processor chip also pushes other network functions and their associated power consumption onto the chip. In this paper, we propose a low latency optical switch architecture that minimizes the power consumed on the processor chip for two scenarios: multiple-socket shared memory coherence networks and optical top-of-rack switches for data centers. The switch architecture reduces power consumed on the CMP using a control plane with a simplified send and forget server interface and the use of a hybrid Mach-Zehnder interferometer and semiconductor optical amplifier integrated optical switch with electronic buffering. Results show that the proposed architecture offers a 42% reduction in head latency at low loads compared with a conventional scheduled optical switch as well as offering increased performance for streaming and incast traffic patterns. Power dissipated on the server chip is shown to be reduced by more than 60% compared with a scheduled optical switch architecture with ring resonator switching.

Original languageEnglish
Pages (from-to)A498-A510
Number of pages13
JournalJournal of Optical Communications and Networking
Volume7
Issue number3
Early online date16 Feb 2015
DOIs
Publication statusPublished - 1 Mar 2015

Keywords

  • Assignment and routing algorithms
  • Networks
  • Optical interconnects

ASJC Scopus subject areas

  • Computer Networks and Communications

Cite this

Low latency optical switch for high performance computing with minimized processor energy load [Invited]. / Liu, Shiyun; Cheng, Qixiang; Madarbux, Muhammad Ridwan; Wonfor, Adrian; Penty, Richard V.; White, Ian H.; Watts, Philip M.

In: Journal of Optical Communications and Networking, Vol. 7, No. 3, 01.03.2015, p. A498-A510.

Research output: Contribution to journalArticle

Liu, Shiyun ; Cheng, Qixiang ; Madarbux, Muhammad Ridwan ; Wonfor, Adrian ; Penty, Richard V. ; White, Ian H. ; Watts, Philip M. / Low latency optical switch for high performance computing with minimized processor energy load [Invited]. In: Journal of Optical Communications and Networking. 2015 ; Vol. 7, No. 3. pp. A498-A510.
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