Skip to main navigation Skip to search Skip to main content

Instruction set customization for area-constrained FPGA designs

  • Alok Prakash
  • , Siew-Kei Lam
  • , Christopher T Clarke
  • , Thambipillai Srikanthan
  • Nanyang Technological University

Research output: Chapter or section in a book/report/conference proceedingBook chapter

2   Link opens in a new tab Citations (SciVal)

Abstract

Custom instructions are commonly used to meet the strict design constraints in high performance systems. This paper extends the application space of our previously proposed FPGA-aware custom instruction enumeration and selection technique for area-constrained designs that maximizes the logic utilization of the available FPGA space. Results indicate a factor of 4 improvement in cycle savings over conventional selection techniques and an average runtime reduction of over 31% and 50% in the enumeration and selection phases respectively.
Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2011
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages329-334
Number of pages6
ISBN (Electronic)978-1-4577-1615-7
ISBN (Print)978-1-4577-1616-4
DOIs
Publication statusPublished - 2011
Event24th IEEE International System on Chip Conference, SOCC 2011, September 26, 2011 - September 28, 2011 - Taipei, Taiwan
Duration: 1 Jan 2011 → …

Publication series

NameInternational System on Chip Conference
PublisherIEEE Computer Society

Conference

Conference24th IEEE International System on Chip Conference, SOCC 2011, September 26, 2011 - September 28, 2011
CityTaipei, Taiwan
Period1/01/11 → …

Fingerprint

Dive into the research topics of 'Instruction set customization for area-constrained FPGA designs'. Together they form a unique fingerprint.

Cite this