Instruction set customization for area-constrained FPGA designs

Alok Prakash, Siew-Kei Lam, Christopher T Clarke, Thambipillai Srikanthan

Research output: Chapter in Book/Report/Conference proceedingChapter

2 Citations (Scopus)

Abstract

Custom instructions are commonly used to meet the strict design constraints in high performance systems. This paper extends the application space of our previously proposed FPGA-aware custom instruction enumeration and selection technique for area-constrained designs that maximizes the logic utilization of the available FPGA space. Results indicate a factor of 4 improvement in cycle savings over conventional selection techniques and an average runtime reduction of over 31% and 50% in the enumeration and selection phases respectively.
Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2011
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages329-334
Number of pages6
ISBN (Electronic)978-1-4577-1615-7
ISBN (Print)978-1-4577-1616-4
DOIs
Publication statusPublished - 2011
Event24th IEEE International System on Chip Conference, SOCC 2011, September 26, 2011 - September 28, 2011 - Taipei, Taiwan
Duration: 1 Jan 2011 → …

Publication series

NameInternational System on Chip Conference
PublisherIEEE Computer Society

Conference

Conference24th IEEE International System on Chip Conference, SOCC 2011, September 26, 2011 - September 28, 2011
CityTaipei, Taiwan
Period1/01/11 → …

Fingerprint

Field programmable gate arrays (FPGA)
Space applications

Cite this

Prakash, A., Lam, S-K., Clarke, C. T., & Srikanthan, T. (2011). Instruction set customization for area-constrained FPGA designs. In Proceedings - IEEE International SOC Conference, SOCC 2011 (pp. 329-334). (International System on Chip Conference). Piscataway, NJ: IEEE. https://doi.org/10.1109/socc.2011.6085114

Instruction set customization for area-constrained FPGA designs. / Prakash, Alok; Lam, Siew-Kei; Clarke, Christopher T; Srikanthan, Thambipillai.

Proceedings - IEEE International SOC Conference, SOCC 2011. Piscataway, NJ : IEEE, 2011. p. 329-334 (International System on Chip Conference).

Research output: Chapter in Book/Report/Conference proceedingChapter

Prakash, A, Lam, S-K, Clarke, CT & Srikanthan, T 2011, Instruction set customization for area-constrained FPGA designs. in Proceedings - IEEE International SOC Conference, SOCC 2011. International System on Chip Conference, IEEE, Piscataway, NJ, pp. 329-334, 24th IEEE International System on Chip Conference, SOCC 2011, September 26, 2011 - September 28, 2011, Taipei, Taiwan, 1/01/11. https://doi.org/10.1109/socc.2011.6085114
Prakash A, Lam S-K, Clarke CT, Srikanthan T. Instruction set customization for area-constrained FPGA designs. In Proceedings - IEEE International SOC Conference, SOCC 2011. Piscataway, NJ: IEEE. 2011. p. 329-334. (International System on Chip Conference). https://doi.org/10.1109/socc.2011.6085114
Prakash, Alok ; Lam, Siew-Kei ; Clarke, Christopher T ; Srikanthan, Thambipillai. / Instruction set customization for area-constrained FPGA designs. Proceedings - IEEE International SOC Conference, SOCC 2011. Piscataway, NJ : IEEE, 2011. pp. 329-334 (International System on Chip Conference).
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