Custom instructions are commonly used to meet the strict design constraints in high performance systems. This paper extends the application space of our previously proposed FPGA-aware custom instruction enumeration and selection technique for area-constrained designs that maximizes the logic utilization of the available FPGA space. Results indicate a factor of 4 improvement in cycle savings over conventional selection techniques and an average runtime reduction of over 31% and 50% in the enumeration and selection phases respectively.
|Name||International System on Chip Conference|
|Publisher||IEEE Computer Society|
|Conference||24th IEEE International System on Chip Conference, SOCC 2011, September 26, 2011 - September 28, 2011|
|Period||1/01/11 → …|