TY - JOUR
T1 - Innovative teaching of IC design and manufacture using the superchip platform
AU - Wilson, P. R.
AU - Wilcock, R.
AU - McNally, I.
AU - Swabey, M.
PY - 2010
Y1 - 2010
N2 - In this paper we describe how an intelligent chip architecture has allowed a large cohort of undergraduate students to be given effective practical insight into IC design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the ?Superchip?, has been developed, which allows multiple student designs to be fabricated on a single IC, and encapsulated in a standard package without excessive cost in terms of time or resources. We demonstrate how the practical process has been tightly coupled with theoretical aspects of the degree course and how transferable skills are incorporated into the design exercise. Furthermore, the students are introduced at an early stage to the key concepts of team working, exposure to real deadlines and collaborative report writing. This paper provides details of the teaching rationale, design exercise overview, design process, chip architecture and test regime.
AB - In this paper we describe how an intelligent chip architecture has allowed a large cohort of undergraduate students to be given effective practical insight into IC design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the ?Superchip?, has been developed, which allows multiple student designs to be fabricated on a single IC, and encapsulated in a standard package without excessive cost in terms of time or resources. We demonstrate how the practical process has been tightly coupled with theoretical aspects of the degree course and how transferable skills are incorporated into the design exercise. Furthermore, the students are introduced at an early stage to the key concepts of team working, exposure to real deadlines and collaborative report writing. This paper provides details of the teaching rationale, design exercise overview, design process, chip architecture and test regime.
UR - http://dx.doi.org/10.1109/TE.2009.2017271
U2 - 10.1109/TE.2009.2017271
DO - 10.1109/TE.2009.2017271
M3 - Article
VL - 53
SP - 297
EP - 305
JO - IEEE Transactions on Education
JF - IEEE Transactions on Education
IS - 2
ER -