Abstract
The choice facing most VCO and PLL designers in modern CMOS processes is whether to use LC oscillators with large area and low phase noise, or to use an inverter based all transistor solution with poor phase noise, but much smaller size. This paper makes significant progress in closing the gap in performance between the inverter based and LC approaches. A novel double feedback dual inverter delay cell is proposed that achieves a significantly wider tuning range than previously reported whilst maintaining excellent phase noise performance. A design methodology is presented that includes noise analysis relating transistor level dimensions to the predicted phase noise performance. Two 120nm 1.2V design examples demonstrate that VCOs based on the improved delay cell can reach frequencies in excess of 6.7GHz, and that tuning ranges of over 7 octaves can be achieved.
Original language | English |
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Title of host publication | IEEE International Symposium on Circuits and Systems (ISCAS), 2008 |
Editors | Ke Li, Reuben Wilcock, Peter Wilson |
Publisher | IEEE |
Pages | 444-447 |
ISBN (Print) | 9781424416837 |
DOIs | |
Publication status | Published - 1 May 2008 |
Event | IEEE International Symposium on Circuits and Systems (ISCAS 2008) - Seattle, WA, USA United States Duration: 18 May 2008 → 21 May 2008 |
Conference
Conference | IEEE International Symposium on Circuits and Systems (ISCAS 2008) |
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Country/Territory | USA United States |
City | Seattle, WA |
Period | 18/05/08 → 21/05/08 |
Keywords
- Oscillator, Phase Noise, Jitter, CMOS, VCO, Tuning Range