Improved 6.7GHz CMOS VCO delay cell with up to seven octave tuning range

Ke Li, R. Wilcock, P. Wilson

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The choice facing most VCO and PLL designers in modern CMOS processes is whether to use LC oscillators with large area and low phase noise, or to use an inverter based all transistor solution with poor phase noise, but much smaller size. This paper makes significant progress in closing the gap in performance between the inverter based and LC approaches. A novel double feedback dual inverter delay cell is proposed that achieves a significantly wider tuning range than previously reported whilst maintaining excellent phase noise performance. A design methodology is presented that includes noise analysis relating transistor level dimensions to the predicted phase noise performance. Two 120nm 1.2V design examples demonstrate that VCOs based on the improved delay cell can reach frequencies in excess of 6.7GHz, and that tuning ranges of over 7 octaves can be achieved.
Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems (ISCAS), 2008
EditorsKe Li, Reuben Wilcock, Peter Wilson
PublisherIEEE
Pages444-447
ISBN (Print)9781424416837
DOIs
Publication statusPublished - 1 May 2008
EventIEEE International Symposium on Circuits and Systems (ISCAS 2008) - Seattle, WA, USA United States
Duration: 18 May 200821 May 2008

Conference

ConferenceIEEE International Symposium on Circuits and Systems (ISCAS 2008)
CountryUSA United States
CitySeattle, WA
Period18/05/0821/05/08

Keywords

  • Oscillator, Phase Noise, Jitter, CMOS, VCO, Tuning Range

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    Li, K., Wilcock, R., & Wilson, P. (2008). Improved 6.7GHz CMOS VCO delay cell with up to seven octave tuning range. In K. Li, R. Wilcock, & P. Wilson (Eds.), IEEE International Symposium on Circuits and Systems (ISCAS), 2008 (pp. 444-447). IEEE. https://doi.org/10.1109/ISCAS.2008.4541450