Implementing area-time efficient VLSI residue to binary converters

T Srikanthan, M Bhardwaj, Christopher T Clarke

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

In this paper, the authors present highly area-time efficient VLSI implementations of residue reverse converters called Compressed Multiply ACcumulate (CMAC) converters. The efficiency results from identifying and eliminating redundancy in previously reported designs. Specifically, the partial sum. Generation and addition are merged into a single carry save addition operation. Also, module multipliers are replaced by simple adders by the bit unfolding and uncorrected residues technique. The analysis of the various implementation options (CPA, CLA or serial) presented here will aid system designers in choosing a reverse converter that conforms to the time, area and power requirements imposed by a given application
Original languageEnglish
Pages163-172
Number of pages10
Publication statusPublished - Nov 1997
EventIEEE Workshop on Signal Processing Systems - Design and Implementation (SIPS 97) - Leicester, UK United Kingdom
Duration: 5 Nov 1997 → …

Conference

ConferenceIEEE Workshop on Signal Processing Systems - Design and Implementation (SIPS 97)
CountryUK United Kingdom
CityLeicester
Period5/11/97 → …

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Keywords

  • binary converters
  • area-time efficient
  • module multipliers
  • CMAC
  • digital signal processing chips
  • carry save addition
  • residue number systems
  • reverse converter
  • VLSI
  • Compressed Multiply ACcumulate
  • residue reverse converters
  • convertors

Cite this

Srikanthan, T., Bhardwaj, M., & Clarke, C. T. (1997). Implementing area-time efficient VLSI residue to binary converters. 163-172. Paper presented at IEEE Workshop on Signal Processing Systems - Design and Implementation (SIPS 97), Leicester, UK United Kingdom.