Abstract
In this paper, the authors present highly area-time efficient VLSI implementations of residue reverse converters called Compressed Multiply ACcumulate (CMAC) converters. The efficiency results from identifying and eliminating redundancy in previously reported designs. Specifically, the partial sum. Generation and addition are merged into a single carry save addition operation. Also, module multipliers are replaced by simple adders by the bit unfolding and uncorrected residues technique. The analysis of the various implementation options (CPA, CLA or serial) presented here will aid system designers in choosing a reverse converter that conforms to the time, area and power requirements imposed by a given application
| Original language | English |
|---|---|
| Pages | 163-172 |
| Number of pages | 10 |
| Publication status | Published - Nov 1997 |
| Event | IEEE Workshop on Signal Processing Systems - Design and Implementation (SIPS 97) - Leicester, UK United Kingdom Duration: 5 Nov 1997 → … |
Conference
| Conference | IEEE Workshop on Signal Processing Systems - Design and Implementation (SIPS 97) |
|---|---|
| Country/Territory | UK United Kingdom |
| City | Leicester |
| Period | 5/11/97 → … |
Keywords
- binary converters
- area-time efficient
- module multipliers
- CMAC
- digital signal processing chips
- carry save addition
- residue number systems
- reverse converter
- VLSI
- Compressed Multiply ACcumulate
- residue reverse converters
- convertors