Implementing area-time efficient VLSI residue to binary converters

T Srikanthan, M Bhardwaj, Christopher T Clarke

Research output: Contribution to conferencePaper

  • 1 Citations

Abstract

In this paper, the authors present highly area-time efficient VLSI implementations of residue reverse converters called Compressed Multiply ACcumulate (CMAC) converters. The efficiency results from identifying and eliminating redundancy in previously reported designs. Specifically, the partial sum. Generation and addition are merged into a single carry save addition operation. Also, module multipliers are replaced by simple adders by the bit unfolding and uncorrected residues technique. The analysis of the various implementation options (CPA, CLA or serial) presented here will aid system designers in choosing a reverse converter that conforms to the time, area and power requirements imposed by a given application

Conference

ConferenceIEEE Workshop on Signal Processing Systems - Design and Implementation (SIPS 97)
CountryUK United Kingdom
CityLeicester
Period5/11/97 → …

Fingerprint

Adders
Redundancy

Keywords

  • binary converters
  • area-time efficient
  • module multipliers
  • CMAC
  • digital signal processing chips
  • carry save addition
  • residue number systems
  • reverse converter
  • VLSI
  • Compressed Multiply ACcumulate
  • residue reverse converters
  • convertors

Cite this

Srikanthan, T., Bhardwaj, M., & Clarke, C. T. (1997). Implementing area-time efficient VLSI residue to binary converters. 163-172. Paper presented at IEEE Workshop on Signal Processing Systems - Design and Implementation (SIPS 97), Leicester, UK United Kingdom.

Implementing area-time efficient VLSI residue to binary converters. / Srikanthan, T; Bhardwaj, M; Clarke, Christopher T.

1997. 163-172 Paper presented at IEEE Workshop on Signal Processing Systems - Design and Implementation (SIPS 97), Leicester, UK United Kingdom.

Research output: Contribution to conferencePaper

Srikanthan, T, Bhardwaj, M & Clarke, CT 1997, 'Implementing area-time efficient VLSI residue to binary converters' Paper presented at IEEE Workshop on Signal Processing Systems - Design and Implementation (SIPS 97), Leicester, UK United Kingdom, 5/11/97, pp. 163-172.
Srikanthan T, Bhardwaj M, Clarke CT. Implementing area-time efficient VLSI residue to binary converters. 1997. Paper presented at IEEE Workshop on Signal Processing Systems - Design and Implementation (SIPS 97), Leicester, UK United Kingdom.
Srikanthan, T ; Bhardwaj, M ; Clarke, Christopher T. / Implementing area-time efficient VLSI residue to binary converters. Paper presented at IEEE Workshop on Signal Processing Systems - Design and Implementation (SIPS 97), Leicester, UK United Kingdom.10 p.
@conference{44129372d3474232ab92dd8a1effbeb8,
title = "Implementing area-time efficient VLSI residue to binary converters",
abstract = "In this paper, the authors present highly area-time efficient VLSI implementations of residue reverse converters called Compressed Multiply ACcumulate (CMAC) converters. The efficiency results from identifying and eliminating redundancy in previously reported designs. Specifically, the partial sum. Generation and addition are merged into a single carry save addition operation. Also, module multipliers are replaced by simple adders by the bit unfolding and uncorrected residues technique. The analysis of the various implementation options (CPA, CLA or serial) presented here will aid system designers in choosing a reverse converter that conforms to the time, area and power requirements imposed by a given application",
keywords = "binary converters, area-time efficient, module multipliers, CMAC, digital signal processing chips, carry save addition, residue number systems, reverse converter, VLSI, Compressed Multiply ACcumulate, residue reverse converters, convertors",
author = "T Srikanthan and M Bhardwaj and Clarke, {Christopher T}",
year = "1997",
month = "11",
language = "English",
pages = "163--172",
note = "IEEE Workshop on Signal Processing Systems - Design and Implementation (SIPS 97) ; Conference date: 05-11-1997",

}

TY - CONF

T1 - Implementing area-time efficient VLSI residue to binary converters

AU - Srikanthan,T

AU - Bhardwaj,M

AU - Clarke,Christopher T

PY - 1997/11

Y1 - 1997/11

N2 - In this paper, the authors present highly area-time efficient VLSI implementations of residue reverse converters called Compressed Multiply ACcumulate (CMAC) converters. The efficiency results from identifying and eliminating redundancy in previously reported designs. Specifically, the partial sum. Generation and addition are merged into a single carry save addition operation. Also, module multipliers are replaced by simple adders by the bit unfolding and uncorrected residues technique. The analysis of the various implementation options (CPA, CLA or serial) presented here will aid system designers in choosing a reverse converter that conforms to the time, area and power requirements imposed by a given application

AB - In this paper, the authors present highly area-time efficient VLSI implementations of residue reverse converters called Compressed Multiply ACcumulate (CMAC) converters. The efficiency results from identifying and eliminating redundancy in previously reported designs. Specifically, the partial sum. Generation and addition are merged into a single carry save addition operation. Also, module multipliers are replaced by simple adders by the bit unfolding and uncorrected residues technique. The analysis of the various implementation options (CPA, CLA or serial) presented here will aid system designers in choosing a reverse converter that conforms to the time, area and power requirements imposed by a given application

KW - binary converters

KW - area-time efficient

KW - module multipliers

KW - CMAC

KW - digital signal processing chips

KW - carry save addition

KW - residue number systems

KW - reverse converter

KW - VLSI

KW - Compressed Multiply ACcumulate

KW - residue reverse converters

KW - convertors

M3 - Paper

SP - 163

EP - 172

ER -