High-speed replicating current comparators for analog convolutional decoders

Andreas Demosthenous, John Taylor

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

This paper describes two high-speed replicating current comparators (RCCs) for use in convolutional decoders. One RCC operates asynchronously by means of a negative feedback mechanism that provides an accurate virtual ground for input current summation and comparison. This circuit requires realization in BiCMOS technology. The other RCC is synchronous and can be implemented using a digital CMOS process. Since this RCC requires positive feedback, resetting is required after each operating cycle. In addition to replicating the “winner,” both types of RCCs identify the winning input by means of a digital binary output voltage. The RCCs were fabricated in a 0.8 μm BiCMOS process and feature a maximum input signal range in excess of 200 μA. The asynchronous RCC operates at speeds up to about 200 MHz, has a resolution of 2 μA, and consumes 5.8 mW from a 2.8 V power supply. The synchronous RCC operates up to about 100 MHz, has a resolution of 1.2 μA, and consumes 2.5 mW from a 3 V power supply. The measurements are compared with post-layout simulations
Original languageEnglish
Pages (from-to)1405-1412
JournalIEEE Transactions on Circuits and Systems Part II: Analog and Digital Signal Processing
Volume47
Issue number12
DOIs
Publication statusPublished - Dec 2000

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High-speed replicating current comparators for analog convolutional decoders. / Demosthenous, Andreas; Taylor, John.

In: IEEE Transactions on Circuits and Systems Part II: Analog and Digital Signal Processing , Vol. 47, No. 12, 12.2000, p. 1405-1412.

Research output: Contribution to journalArticle

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