Abstract
This paper presents method to implement Linear Back Projection (LBP) algorithm in Field Programmable Gate Arrays (FPGA). Top-down approach has been adopted for the design of the hardware of LBP algorithm. The FPGA used is Xilinx Spartan 3A and the language used to design the hardware is VHSIC Hardware Description Language (VHDL). The final design is able to reconstruct a 32×32 pixel image from 8-electrode Electrical Capacitance Tomography (ECT) with speed of 23809 slice images per second and the image is shown on LCD. It could be further extended to form quasi 3D image with 32 slices at rate 744 frame-per-second.
Original language | English |
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Title of host publication | Proceedings - 2015 4th International Conference on Instrumentation, Communications, Information Technology and Biomedical Engineering, ICICI-BME 2015 |
Place of Publication | Bandung |
Publisher | IEEE |
Pages | 124-129 |
Number of pages | 6 |
ISBN (Electronic) | 9781467378000 |
ISBN (Print) | 978-1-4673-7801-7 |
DOIs | |
Publication status | Published - 11 Feb 2016 |
Event | 4th International Conference on Instrumentation, Communications, Information Technology and Biomedical Engineering, ICICI-BME 2015 - Bandung, Indonesia Duration: 2 Nov 2015 → 3 Nov 2015 |
Conference
Conference | 4th International Conference on Instrumentation, Communications, Information Technology and Biomedical Engineering, ICICI-BME 2015 |
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Country/Territory | Indonesia |
City | Bandung |
Period | 2/11/15 → 3/11/15 |
Keywords
- capacitance tomography
- FPGA
- linear back-projection
- VHDL
ASJC Scopus subject areas
- Computer Networks and Communications
- Information Systems
- Biomedical Engineering
- Instrumentation