A 533 MHz programmable phase-locked loop is designed for DDR applications using a switched current filter and implicit phase detection. The use of switched current technology allows a fully integrated loop filter which is much smaller than equivalent integrated passive filters, as a result the circuit occupies only 0.012 mm2 on a 0.12 m 1.2 V digital CMOS process.

Original languageEnglish
Pages (from-to)1297-1299
Number of pages3
JournalElectronics Letters
Issue number22
Publication statusPublished - 2008

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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