Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration

S. K. Lam, T. Srikanthan, C.T. Clarke

Research output: Chapter in Book/Report/Conference proceedingOther chapter contribution

4 Citations (Scopus)

Abstract

Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, without compromising on performance. We present a framework that aims to increase the advantages of runtime reconfiguration on reconfigurable processors that support full or partial runtime reconfiguration. The proposed framework incorporates a hierarchical loop partitioning strategy that leverages FPGA-aware merging of custom instructions to: 1) maximize the reconfigurable logic block utilization in each configuration, and 2) reduce the runtime reconfiguration overhead. Experimental results show that the proposed strategy leads to over 39% average reduction in runtime reconfiguration overhead for partial runtime reconfiguration. In addition, the proposed strategy leads to an average performance gain of over 32% and 34% for full and partial runtime reconfiguration respectively.
Original languageEnglish
Title of host publicationReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings
PublisherIEEE
DOIs
Publication statusPublished - 2012
Event7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip - York, UK United Kingdom
Duration: 9 Jul 201211 Jul 2012

Conference

Conference7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip
CountryUK United Kingdom
CityYork
Period9/07/1211/07/12

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