Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration

S.-K. Lam, C.T. Clarke, T. Srikanthan

Research output: Contribution to journalArticle

Abstract

Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, without compromising on performance. We present a framework that aims to increase the performance benefits of reconfigurable processors that support full or partial runtime reconfiguration. The proposed framework achieves this by: (1) providing a means for choosing suitable custom instruction selection heuristics, (2) leveraging FPGA-awaremerging of custom instructions to maximize the reconfigurable logic block utilization in each configuration, and (3) incorporating a hierarchical loop partitioning strategy to reduce runtime reconfiguration overhead. We show that the performance gain can be improved by employing suitable custom instruction selection heuristics that, in turn, depend on the reconfigurable resource constraints and the merging factor (extent to which the selected custom instructions can be merged). The hierarchical loop partitioning strategy leads to an average performance gain of over 31% and 46% for full and partial runtime reconfiguration, respectively. Performance gain can be further increased to over 52% and 70% for full and partial runtime reconfiguration, respectively, by exploiting FPGA-aware merging of custom instructions.
LanguageEnglish
Article number26
Pages1 - 15
Number of pages15
JournalACM Transactions on Reconfigurable Technology and Systems
Volume7
Issue number3
DOIs
StatusPublished - Aug 2014

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Merging
Field programmable gate arrays (FPGA)
Embedded systems
Computer hardware
Costs

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Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration. / Lam, S.-K.; Clarke, C.T.; Srikanthan, T.

In: ACM Transactions on Reconfigurable Technology and Systems, Vol. 7, No. 3, 26, 08.2014, p. 1 - 15.

Research output: Contribution to journalArticle

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