This study explores the benefits of the Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Array (FPGA) based System on Chip (SoC) architectures. Consideration is given to the constraints imposed by the implementation of partial reconfiguration on both pre-emptible context switching and continuous end-to-end dataflow applications. Skeleton structure systems that permit the insertion and removal of ‘blocks’ into the overall FPGA floorplan have been developed. These can be reconfigured dynamically by the on chip system hosteven during data processing. In pre-emptible context switching maintaining the execution state of a design before switching away from it becomes of paramount importance; this work presents a new Pre-emptible Flip Flop (PFF) design that is used as a basis for a Task Specific Access Structure (TSAS) for FPGA designs and then proposes an algorithm to automate the insertion of these PFF’s into a synthesised design. Expanding into continuous dataflow application design allows the system host to re-route signals during the partial reconfiguration process and then re-establish the processing chain with the new configuration hence maintaining a continuous uninterrupted dataflow.The design flow used in this work makes use of non-standard IP and tools that are not supported by Altera for the Cyclone V SoC. However, as this paper shows, partial reconfiguration is possible inside the Cyclone V SoC device.For further information please contact the authors.
|Publication status||Published - 6 Nov 2015|
|Event||Altera SoC Developers Forum - steigenberger airport hotel, Frankfurt, UK United Kingdom|
Duration: 14 Oct 2015 → 14 Oct 2015
|Conference||Altera SoC Developers Forum|
|Country/Territory||UK United Kingdom|
|Period||14/10/15 → 14/10/15|