Designing Multi-Level Resistance States in Graphene Ferroelectric Transistors

Morteza Hassanpour Amiri, Jonas Heidler, Klaus Müllen, Paschalis Gkoupidenis, Kamal Asadi

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Conventional memory elements code information in the Boolean “0” and “1” form. Devices that exceed bistability in their resistance are useful as memory for future data storage due to their enhanced memory capacity, and are also a necessity for contemporary applications such as neuromorphic computing. Here, with the aid of an experimentally validated device model, design rules are outlined and more than two stable resistance states in a graphene ferroelectric field-effect transistor are experimentally demonstrated. The design methodology can be extrapolated for on-demand introduction of multiple resistance states in ferroelectric transistors for applications both in data storage and neuromorphic computing.

Original languageEnglish
Article number2003085
JournalAdvanced Functional Materials
Volume30
Issue number34
DOIs
Publication statusPublished - 1 Aug 2020

Keywords

  • field-effect transistors
  • graphene
  • multi-bit memory
  • neuromorphic computing

ASJC Scopus subject areas

  • Chemistry(all)
  • Materials Science(all)
  • Condensed Matter Physics

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