TY - JOUR
T1 - Design of a low-noise preamplifier for nerve cuff electrode recording
AU - Rieger, R
AU - Taylor, J
AU - Demosthenous, A
AU - Donaldson, N
AU - Langlois, P J
N1 - ID number: ISI:000184371400008
PY - 2003
Y1 - 2003
N2 - This paper discusses certain important issues involved in the design of a nerve signal preamplifier for implantable neuroprostheses. Since the electroneurograin signal measured from cuff electrodes is typically on the order of 1 uV, a very low-noise interface is essential. We present the argument for the use of BiCMOS technology in, this application and then, describe the design and evaluation of a complete preamplifier fabricated in a 0.8-mum double-metal double-poly process. The preamplifier has, a nominal voltage gain of 100, a bandwidth of 15 kHz; and a measured equivalent input-referred noise voltage spectral density of 3.3 nV/rootHz at 1 kHz. The total input-referred rms noise voltage in a bandwidth 1 Hz-10 kHz is 290 nV, the power consumption is 1.3 mW from +/-2.5-V power supplies, and the active area is 0.3 mm(2).
AB - This paper discusses certain important issues involved in the design of a nerve signal preamplifier for implantable neuroprostheses. Since the electroneurograin signal measured from cuff electrodes is typically on the order of 1 uV, a very low-noise interface is essential. We present the argument for the use of BiCMOS technology in, this application and then, describe the design and evaluation of a complete preamplifier fabricated in a 0.8-mum double-metal double-poly process. The preamplifier has, a nominal voltage gain of 100, a bandwidth of 15 kHz; and a measured equivalent input-referred noise voltage spectral density of 3.3 nV/rootHz at 1 kHz. The total input-referred rms noise voltage in a bandwidth 1 Hz-10 kHz is 290 nV, the power consumption is 1.3 mW from +/-2.5-V power supplies, and the active area is 0.3 mm(2).
U2 - 10.1109/jssc.2003.814437
DO - 10.1109/jssc.2003.814437
M3 - Article
SN - 0018-9200
VL - 38
SP - 1373
EP - 1379
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 8
ER -