Design of a low-cost 10 Gb/s chip-to-chip optical interconnect

Aeffendi Hashim, Nikolaos Bamiedakis, Ying Hao, Richard V. Penty, Ian H. White

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The design of a low-cost chip-to-chip optical interconnect is presented. A ray tracing model is used to investigate the sensitivity of the optical coupling efficiency to misalignments of the optical components. Estimation of the power budget predicts operation at 10 Gb/s with a noise margin of 6.3 dB.

Original languageEnglish
Title of host publication2010 International Conference on Photonics, ICP2010
DOIs
Publication statusPublished - 22 Nov 2010
Event2010 1st International Conference on Photonics, ICP2010 - Langkawi, Kedah, Malaysia
Duration: 5 Jul 20107 Jul 2010

Conference

Conference2010 1st International Conference on Photonics, ICP2010
CountryMalaysia
CityLangkawi, Kedah
Period5/07/107/07/10

Keywords

  • Optical coupling efficiency
  • Optical interconnections
  • Polymer waveguide
  • Ray tracing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Hashim, A., Bamiedakis, N., Hao, Y., Penty, R. V., & White, I. H. (2010). Design of a low-cost 10 Gb/s chip-to-chip optical interconnect. In 2010 International Conference on Photonics, ICP2010 [5604391] https://doi.org/10.1109/ICP.2010.5604391