Design and analysis of phase locked loops using behavioral modeling and mixed mode simulation techniques

In modern consumer electronics and communications applications, the Phase Locked Loop (PLL) is a central component of these designs. The PLL circuit is not a new concept and in fact has been used for over 60 years after its invention for the synchronous reception of radio signals. The widespread use of the circuit is due to its ease of use and also the compact nature of the final IC. Designers have been using various simulation tools and methods to model and simulate PLLs at different levels. For example at the system level MatrixX, Saber, Matlab and high level languages such as C or FORTRAN have been used to analyze the loop response, while digital simulators have been used to examine the time domain response of the purely digital PLLs using gate level, Verilog or VHDL descriptions. Mixed mode simulators such as Saber have been used to analyze the mixed signal and mixed level aspects of the design and finally analogue simulators such as Spice have been applied to the lowest transistor level simulations of the final IC design. The unfortunate problem in general for designers has been the lack of an integrated approach allowing all of these different methods to be applied to the same physical design with a resulting discontinuity in the design process. This paper will show how by applying behavioral modeling techniques to abstract models to different levels and by the effective use of mixed signal modeling a more coherent design process can be applied with the resulting improvement in the robustness and reliability of the final design.