Delay test for diagnosis of power switches

S. Khursheed, K. Shi, B. M. Al-Hashimi, P. R. Wilson, K. Chakrabarty

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge, this is the first work in open-literature to show a systematic diagnosis method for accurately diagnosing power switches. The proposed diagnosis method utilizes recently proposed DFT solution for efficient testing of power switches in the presence of PVT variation. It divides power switches into segments such that any faulty power switch is detectable thereby achieving high diagnosis accuracy. The proposed diagnosis method has been validated through SPICE simulation using a number of ISCAS benchmarks synthesized with a 90-nm gate library. Simulation results show that when considering the influence of process variation, the worst case loss of accuracy is less than 4.5 and the worst case loss of accuracy is less than 12% when considering VT (Voltage and Temperature) variations.
Original languageEnglish
Pages (from-to)197-206
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume22
Issue number2
DOIs
Publication statusPublished - Feb 2014

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Switches
SPICE
Discrete Fourier transforms
Testing
Electric potential
Temperature

Keywords

  • sleep transistor, diagnosis, power gating, leakage power management, design for test (dft)

Cite this

Delay test for diagnosis of power switches. / Khursheed, S.; Shi, K.; Al-Hashimi, B. M.; Wilson, P. R.; Chakrabarty, K.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 2, 02.2014, p. 197-206.

Research output: Contribution to journalArticle

Khursheed, S. ; Shi, K. ; Al-Hashimi, B. M. ; Wilson, P. R. ; Chakrabarty, K. / Delay test for diagnosis of power switches. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014 ; Vol. 22, No. 2. pp. 197-206.
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