This paper describes an integrated circuit (ASIC) implementing the core functionality for the technique of velocity selective recording (VSR) of ENG in which multiple neural signals are matched and summed to identify excited axon populations in terms of velocity. Delay matching is achieved using multiple sample-and-hold blocks arranged to realize a matching range between 10-100 μs for eight input channels (80 μs-800 μs total delay) as well as signal summation. The system laid out in 0.35 μm CMOS technology occupies 0.78 mm2 core area and consumes 30 μW of power from a 3 V supply. A buffer driver stage is added which consumes 150 μW. Simulated results are provided to confirm that the velocity spectrum is successfully extracted using the proposed system.
|Publication status||Published - 2014|
|Event||2014 IEEE Asia Pacific Conference on Circuits and Systems - Ishigaki , Japan|
Duration: 17 Nov 2014 → 20 Nov 2014
|Conference||2014 IEEE Asia Pacific Conference on Circuits and Systems|
|Period||17/11/14 → 20/11/14|
Rieger, R., & Taylor, J. (2014). Delay-line-based signal processing ASIC for velocity selective nerve recording. 205-208. Paper presented at 2014 IEEE Asia Pacific Conference on Circuits and Systems, Ishigaki , Japan. https://doi.org/10.1109/APCCAS.2014.7032757