Traditionally, Instruction set extension (ISE) algorithms have treated memory and control flow as invalid operations during custom instruction identification to ensure deterministic latency of these extended instructions. In order to overcome these constraints some work has been done to incorporate local memory for custom instructions with memory operations. Such architectures have invariably relied on the expensive DMA protocol for data transfer. Cache-coherence management poses another challenge in such systems and requires additional hardware and/or software intervention. We propose a novel custom instruction architecture capable of incorporating certain types of memory and control-flow operations. Unlike existing architectures, the proposed design eliminates the need for expensive Direct Memory Access (DMA) transfers and additional cache management sub-systems, thereby saving significant time and energy. Our method is focused mainly on accelerating code segments with static variables as well as the ones allocated on the stack, which are widely prevalent in embedded applications. Experimental results show that the proposed method achieves a substantial performance gain of upto 47% over base processor implementation.
|Title of host publication||22nd International Conference on Field Programmable Logic and Applications, FPL 2012|
|Number of pages||4|
|Publication status||Published - Aug 2012|
|Event||22nd International Conference on Field Programmable Logic and Applications - Oslo, Norway|
Duration: 28 Aug 2012 → 30 Aug 2012
|Conference||22nd International Conference on Field Programmable Logic and Applications|
|Period||28/08/12 → 30/08/12|