Current mode techniques for multiple valued arithmetic and logic

Christopher T Clarke; G R Nudd; S Summerfield

doi:10.1109/ISCAS.1994.409251

Current mode techniques for multiple valued arithmetic and logic

Christopher T Clarke, G R Nudd, S Summerfield

Department of Electronic & Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper analyses the general properties of Current Mode Multiple Valued Logic (CMMVL) circuits, and presents a framework for further exploitation. A unified circuit view is proposed in which circuits are described in terms of CMMVL to voltage mode binary decoders, and binary to CMMVL encoders. The relative merits of various encodings are explored for a single digit multiplier. It is shown that CMMVL has an inherent advantage in the VLSI layout of fan-in dominated subsystems such as Wallace trees. The construction of CMMVL circuit cells for general logic is discussed

Original language	English
Pages	279-282
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.1994.409251
Publication status	Published - 1994
Event	IEEE International Symposium on Circuits and Systems (ISCAS '94) - London, UK United Kingdom Duration: 30 May 1994 → 2 Jun 1994

Conference

Conference	IEEE International Symposium on Circuits and Systems (ISCAS '94)
Country/Territory	UK United Kingdom
City	London
Period	30/05/94 → 2/06/94

Bibliographical note

Vol 4

Keywords

binary to CMMVL encoders
decoders
current mode techniques
VLSI
logic design
multivalued logic circuits
adders
multiple valued logic
digital arithmetic
MVL circuits
VLSI layout
multiple valued arithmetic
integrated logic circuits
CMMVL circuit cells
Wallace trees
decoding
multiplying circuits
current mode multiple valued logic
single digit multiplier
encoding
fan-in dominated subsystems

Access to Document

10.1109/ISCAS.1994.409251

Cite this

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title = "Current mode techniques for multiple valued arithmetic and logic",

abstract = "This paper analyses the general properties of Current Mode Multiple Valued Logic (CMMVL) circuits, and presents a framework for further exploitation. A unified circuit view is proposed in which circuits are described in terms of CMMVL to voltage mode binary decoders, and binary to CMMVL encoders. The relative merits of various encodings are explored for a single digit multiplier. It is shown that CMMVL has an inherent advantage in the VLSI layout of fan-in dominated subsystems such as Wallace trees. The construction of CMMVL circuit cells for general logic is discussed",

keywords = "binary to CMMVL encoders, decoders, current mode techniques, VLSI, logic design, multivalued logic circuits, adders, multiple valued logic, digital arithmetic, MVL circuits, VLSI layout, multiple valued arithmetic, integrated logic circuits, CMMVL circuit cells, Wallace trees, decoding, multiplying circuits, current mode multiple valued logic, single digit multiplier, encoding, fan-in dominated subsystems",

author = "Clarke, \{Christopher T\} and Nudd, \{G R\} and S Summerfield",

note = "Vol 4; IEEE International Symposium on Circuits and Systems (ISCAS '94) ; Conference date: 30-05-1994 Through 02-06-1994",

year = "1994",

doi = "10.1109/ISCAS.1994.409251",

language = "English",

pages = "279--282",

}

TY - CONF

T1 - Current mode techniques for multiple valued arithmetic and logic

AU - Clarke, Christopher T

AU - Nudd, G R

AU - Summerfield, S

N1 - Vol 4

PY - 1994

Y1 - 1994

N2 - This paper analyses the general properties of Current Mode Multiple Valued Logic (CMMVL) circuits, and presents a framework for further exploitation. A unified circuit view is proposed in which circuits are described in terms of CMMVL to voltage mode binary decoders, and binary to CMMVL encoders. The relative merits of various encodings are explored for a single digit multiplier. It is shown that CMMVL has an inherent advantage in the VLSI layout of fan-in dominated subsystems such as Wallace trees. The construction of CMMVL circuit cells for general logic is discussed

AB - This paper analyses the general properties of Current Mode Multiple Valued Logic (CMMVL) circuits, and presents a framework for further exploitation. A unified circuit view is proposed in which circuits are described in terms of CMMVL to voltage mode binary decoders, and binary to CMMVL encoders. The relative merits of various encodings are explored for a single digit multiplier. It is shown that CMMVL has an inherent advantage in the VLSI layout of fan-in dominated subsystems such as Wallace trees. The construction of CMMVL circuit cells for general logic is discussed

KW - binary to CMMVL encoders

KW - decoders

KW - current mode techniques

KW - VLSI

KW - logic design

KW - multivalued logic circuits

KW - adders

KW - multiple valued logic

KW - digital arithmetic

KW - MVL circuits

KW - VLSI layout

KW - multiple valued arithmetic

KW - integrated logic circuits

KW - CMMVL circuit cells

KW - Wallace trees

KW - decoding

KW - multiplying circuits

KW - current mode multiple valued logic

KW - single digit multiplier

KW - encoding

KW - fan-in dominated subsystems

UR - http://dx.doi.org/10.1109/ISCAS.1994.409251

UR - https://www.scopus.com/pages/publications/0028594149

U2 - 10.1109/ISCAS.1994.409251

DO - 10.1109/ISCAS.1994.409251

M3 - Paper

SP - 279

EP - 282

T2 - IEEE International Symposium on Circuits and Systems (ISCAS '94)

Y2 - 30 May 1994 through 2 June 1994

ER -

Current mode techniques for multiple valued arithmetic and logic

Abstract

Conference

Bibliographical note

Keywords

Access to Document

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