Control architecture for high capacity ultistage photonic switch circuits

Engineering

• Photonics 100%
• Control Architecture 100%
• Multistage 66%
• Reconfigurability 33%
• Output Power 33%
• Control Scheme 33%
• Fits and Tolerances 33%
• Input Power 33%
• Delay Time 33%
• Dynamic Range 33%
• Input Node 33%
• Optical Path 33%
• Power Penalty 33%
• Optical Power 33%
• Electric Delay Lines 33%
• Power Fluctuation 33%
• Power Transient 33%
• Digital Control 33%
• Output Stage 33%
• Input Path 33%