Clock-modulation based watermark for protection of embedded processors

Jedrzej Kufel, Peter Wilson, Stephen Hill, Bashir Al-Hashimi, Paul N. Whatmough, James Myers

Research output: Contribution to conferencePaper

2 Citations (Scopus)
81 Downloads (Pure)

Abstract

This paper presents a novel watermark generation technique for the protection of embedded processors. In previous work, a load circuit is used to generate detectable watermark patterns in the ASIC power supply. This approach leads to hardware area overheads. We propose removing the dedicated load circuit entirely, instead to compensate the reduced power consumption the watermark power pattern is emulated by reusing existing clock gated sequential logic as a zero-overhead load circuit and modulating the clock-gating enable signal with the watermark sequence. The proposed technique has been validated through experiments using two ASICs in 65nm CMOS, one with an ARM Cortex-M0 microcontroller and one with a Cortex-A5 microprocessor. Silicon measurement results verify the viability of the technique for embedded processors. Furthermore, the proposed clock modulation technique demonstrates a significant area reduction, without compromising the detection performance. In our experiments an area overhead reduction of 98$% was achieved. Through reuse of existing logic and reduction of watermark hardware implementation costs, the proposed clock modulation technique offers an improved robustness against removal attacks
Original languageEnglish
Pages1 - 6
Number of pages6
DOIs
Publication statusPublished - 2014
EventDesign, Automation and Test in Europe Conference and Exhibition (DATE), 2014 - Germany, Dresden, Germany
Duration: 24 Mar 201428 Mar 2014

Conference

ConferenceDesign, Automation and Test in Europe Conference and Exhibition (DATE), 2014
CountryGermany
CityDresden
Period24/03/1428/03/14

Fingerprint

Clocks
Modulation
Application specific integrated circuits
Networks (circuits)
Hardware
Microcontrollers
Microprocessor chips
Electric power utilization
Experiments
Silicon
Costs

Cite this

Kufel, J., Wilson, P., Hill, S., Al-Hashimi, B., Whatmough, P. N., & Myers, J. (2014). Clock-modulation based watermark for protection of embedded processors. 1 - 6. Paper presented at Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , Dresden, Germany. https://doi.org/10.7873/DATE.2014.053

Clock-modulation based watermark for protection of embedded processors. / Kufel, Jedrzej; Wilson, Peter; Hill, Stephen; Al-Hashimi, Bashir; Whatmough, Paul N.; Myers, James.

2014. 1 - 6 Paper presented at Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , Dresden, Germany.

Research output: Contribution to conferencePaper

Kufel, J, Wilson, P, Hill, S, Al-Hashimi, B, Whatmough, PN & Myers, J 2014, 'Clock-modulation based watermark for protection of embedded processors' Paper presented at Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , Dresden, Germany, 24/03/14 - 28/03/14, pp. 1 - 6. https://doi.org/10.7873/DATE.2014.053
Kufel J, Wilson P, Hill S, Al-Hashimi B, Whatmough PN, Myers J. Clock-modulation based watermark for protection of embedded processors. 2014. Paper presented at Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , Dresden, Germany. https://doi.org/10.7873/DATE.2014.053
Kufel, Jedrzej ; Wilson, Peter ; Hill, Stephen ; Al-Hashimi, Bashir ; Whatmough, Paul N. ; Myers, James. / Clock-modulation based watermark for protection of embedded processors. Paper presented at Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , Dresden, Germany.6 p.
@conference{6543adee300645afbf252ff6b5958009,
title = "Clock-modulation based watermark for protection of embedded processors",
abstract = "This paper presents a novel watermark generation technique for the protection of embedded processors. In previous work, a load circuit is used to generate detectable watermark patterns in the ASIC power supply. This approach leads to hardware area overheads. We propose removing the dedicated load circuit entirely, instead to compensate the reduced power consumption the watermark power pattern is emulated by reusing existing clock gated sequential logic as a zero-overhead load circuit and modulating the clock-gating enable signal with the watermark sequence. The proposed technique has been validated through experiments using two ASICs in 65nm CMOS, one with an ARM Cortex-M0 microcontroller and one with a Cortex-A5 microprocessor. Silicon measurement results verify the viability of the technique for embedded processors. Furthermore, the proposed clock modulation technique demonstrates a significant area reduction, without compromising the detection performance. In our experiments an area overhead reduction of 98${\%} was achieved. Through reuse of existing logic and reduction of watermark hardware implementation costs, the proposed clock modulation technique offers an improved robustness against removal attacks",
author = "Jedrzej Kufel and Peter Wilson and Stephen Hill and Bashir Al-Hashimi and Whatmough, {Paul N.} and James Myers",
year = "2014",
doi = "10.7873/DATE.2014.053",
language = "English",
pages = "1 -- 6",
note = "Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 ; Conference date: 24-03-2014 Through 28-03-2014",

}

TY - CONF

T1 - Clock-modulation based watermark for protection of embedded processors

AU - Kufel, Jedrzej

AU - Wilson, Peter

AU - Hill, Stephen

AU - Al-Hashimi, Bashir

AU - Whatmough, Paul N.

AU - Myers, James

PY - 2014

Y1 - 2014

N2 - This paper presents a novel watermark generation technique for the protection of embedded processors. In previous work, a load circuit is used to generate detectable watermark patterns in the ASIC power supply. This approach leads to hardware area overheads. We propose removing the dedicated load circuit entirely, instead to compensate the reduced power consumption the watermark power pattern is emulated by reusing existing clock gated sequential logic as a zero-overhead load circuit and modulating the clock-gating enable signal with the watermark sequence. The proposed technique has been validated through experiments using two ASICs in 65nm CMOS, one with an ARM Cortex-M0 microcontroller and one with a Cortex-A5 microprocessor. Silicon measurement results verify the viability of the technique for embedded processors. Furthermore, the proposed clock modulation technique demonstrates a significant area reduction, without compromising the detection performance. In our experiments an area overhead reduction of 98$% was achieved. Through reuse of existing logic and reduction of watermark hardware implementation costs, the proposed clock modulation technique offers an improved robustness against removal attacks

AB - This paper presents a novel watermark generation technique for the protection of embedded processors. In previous work, a load circuit is used to generate detectable watermark patterns in the ASIC power supply. This approach leads to hardware area overheads. We propose removing the dedicated load circuit entirely, instead to compensate the reduced power consumption the watermark power pattern is emulated by reusing existing clock gated sequential logic as a zero-overhead load circuit and modulating the clock-gating enable signal with the watermark sequence. The proposed technique has been validated through experiments using two ASICs in 65nm CMOS, one with an ARM Cortex-M0 microcontroller and one with a Cortex-A5 microprocessor. Silicon measurement results verify the viability of the technique for embedded processors. Furthermore, the proposed clock modulation technique demonstrates a significant area reduction, without compromising the detection performance. In our experiments an area overhead reduction of 98$% was achieved. Through reuse of existing logic and reduction of watermark hardware implementation costs, the proposed clock modulation technique offers an improved robustness against removal attacks

UR - http://dx.doi.org/10.7873/DATE.2014.053

U2 - 10.7873/DATE.2014.053

DO - 10.7873/DATE.2014.053

M3 - Paper

SP - 1

EP - 6

ER -