Behavioural modeling and simulation of a switched-current phase locked loop

Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Further recent advances indicate that adopting a switched current architecture can lead to equivalent performance but with a significantly reduced area compared to switched capacitor structures. While this is useful in itself, the use of behavioural modeling and simulation at a structural and building block level has allowed architectural exploration and evaluation to be carried out on novel topologies based on this approach. The result is an integrated design flow that uses behavioural models to test the performance of the circuit, leading directly to a synthesized structural model that can be verified using a common design platform. This has the obvious benefit of reducing the full custom analog design effort required when developing topologies and building blocks for new processes. In this paper we describe the design approach of a Phase Locked Loop (PLL) based on a novel Switched-Current (SI) architecture using behavioural models written in VHDL-AMS. Simulations demonstrate the performance of the design at a high level and are used to optimize the behaviour of the loop response with regard to design specifications. The modeling approach is explained, from the basic building blocks used in the SI methodology through to more abstract models of the system architecture. The advantage of using behavioural models is highlighted with the ability to carry out parametric analysis and statistical analysis to investigate tolerances, adherence to specifications and parameter variations. The resulting simulations are consistent with transistor level simulation results, but several orders of magnitude faster. The resulting design achieves a performance that is comparable with designs using current techniques but with significantly reduced area.