ARM/THUMB code compression for embedded systems

X H Xu, S R Jones, C T Clarke

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Abstract

The use of code compression in embedded systems based on standard RISC instruction set architectures (ISA) has been shown in the past to be of benefit in reducing overall system cost. The 16-bit THUMB ISA from ARM Ltd has a significantly higher density than the original 32-bits ARM ISA. In this paper we propose a new memory compression architecture, which employs a lossless data compression algorithm to achieve a further size reduction of around 20% on the THUMB code. We show that in some applications, the decompression can be performed in software on the main system processor without excessive processing time overheads.
Original languageEnglish
Pages32-35
Number of pages4
DOIs
Publication statusPublished - 2003
Event15th International Conference on Microelectronics (ICM 2003) - Cairo, Egypt
Duration: 9 Dec 200311 Dec 2003

Conference

Conference15th International Conference on Microelectronics (ICM 2003)
CountryEgypt
CityCairo
Period9/12/0311/12/03

Keywords

  • size reduction
  • memory compression architecture
  • embedded systems
  • data compression
  • RISC
  • memory architecture
  • data compression algorithm
  • reduced instruction set computing

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  • Cite this

    Xu, X. H., Jones, S. R., & Clarke, C. T. (2003). ARM/THUMB code compression for embedded systems. 32-35. Paper presented at 15th International Conference on Microelectronics (ICM 2003), Cairo, Egypt. https://doi.org/10.1109/ICM.2003.1287715