ARM/THUMB code compression for embedded systems

X H Xu; S R Jones; C T Clarke

doi:10.1109/ICM.2003.1287715

ARM/THUMB code compression for embedded systems

X H Xu, S R Jones, C T Clarke

Department of Electronic & Electrical Engineering

Research output: Contribution to conference › Paper

2 Citations (SciVal)

Abstract

The use of code compression in embedded systems based on standard RISC instruction set architectures (ISA) has been shown in the past to be of benefit in reducing overall system cost. The 16-bit THUMB ISA from ARM Ltd has a significantly higher density than the original 32-bits ARM ISA. In this paper we propose a new memory compression architecture, which employs a lossless data compression algorithm to achieve a further size reduction of around 20% on the THUMB code. We show that in some applications, the decompression can be performed in software on the main system processor without excessive processing time overheads.

Original language	English
Pages	32-35
Number of pages	4
DOIs	https://doi.org/10.1109/ICM.2003.1287715
Publication status	Published - 2003
Event	15th International Conference on Microelectronics (ICM 2003) - Cairo, Egypt Duration: 9 Dec 2003 → 11 Dec 2003

Conference

Conference	15th International Conference on Microelectronics (ICM 2003)
Country/Territory	Egypt
City	Cairo
Period	9/12/03 → 11/12/03

Keywords

size reduction
memory compression architecture
embedded systems
data compression
RISC
memory architecture
data compression algorithm
reduced instruction set computing

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10.1109/ICM.2003.1287715

Cite this

@conference{98b982e4b94e4c46bdd3647235dee27e,

title = "ARM/THUMB code compression for embedded systems",

abstract = "The use of code compression in embedded systems based on standard RISC instruction set architectures (ISA) has been shown in the past to be of benefit in reducing overall system cost. The 16-bit THUMB ISA from ARM Ltd has a significantly higher density than the original 32-bits ARM ISA. In this paper we propose a new memory compression architecture, which employs a lossless data compression algorithm to achieve a further size reduction of around 20% on the THUMB code. We show that in some applications, the decompression can be performed in software on the main system processor without excessive processing time overheads.",

keywords = "size reduction, memory compression architecture, embedded systems, data compression, RISC, memory architecture, data compression algorithm, reduced instruction set computing",

author = "Xu, {X H} and Jones, {S R} and Clarke, {C T}",

year = "2003",

doi = "10.1109/ICM.2003.1287715",

language = "English",

pages = "32--35",

note = "15th International Conference on Microelectronics (ICM 2003) ; Conference date: 09-12-2003 Through 11-12-2003",

}

TY - CONF

T1 - ARM/THUMB code compression for embedded systems

AU - Xu, X H

AU - Jones, S R

AU - Clarke, C T

PY - 2003

Y1 - 2003

N2 - The use of code compression in embedded systems based on standard RISC instruction set architectures (ISA) has been shown in the past to be of benefit in reducing overall system cost. The 16-bit THUMB ISA from ARM Ltd has a significantly higher density than the original 32-bits ARM ISA. In this paper we propose a new memory compression architecture, which employs a lossless data compression algorithm to achieve a further size reduction of around 20% on the THUMB code. We show that in some applications, the decompression can be performed in software on the main system processor without excessive processing time overheads.

AB - The use of code compression in embedded systems based on standard RISC instruction set architectures (ISA) has been shown in the past to be of benefit in reducing overall system cost. The 16-bit THUMB ISA from ARM Ltd has a significantly higher density than the original 32-bits ARM ISA. In this paper we propose a new memory compression architecture, which employs a lossless data compression algorithm to achieve a further size reduction of around 20% on the THUMB code. We show that in some applications, the decompression can be performed in software on the main system processor without excessive processing time overheads.

KW - size reduction

KW - memory compression architecture

KW - embedded systems

KW - data compression

KW - RISC

KW - memory architecture

KW - data compression algorithm

KW - reduced instruction set computing

UR - http://dx.doi.org/10.1109/ICM.2003.1287715

U2 - 10.1109/ICM.2003.1287715

DO - 10.1109/ICM.2003.1287715

M3 - Paper

SP - 32

EP - 35

T2 - 15th International Conference on Microelectronics (ICM 2003)

Y2 - 9 December 2003 through 11 December 2003

ER -

ARM/THUMB code compression for embedded systems

Abstract

Conference

Keywords

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