Area-time-efficient VLSI residue-to-binary converters

T Srikanthan, M Bhardwaj, Christopher T Clarke

Research output: Contribution to journalArticle

  • 10 Citations

Abstract

The authors present highly area-time-efficient VLSI implementations of residue reverse converters called compressed multiply accumulate (CMAC) converters. This efficiency results from carefully identifying and eliminating redundancy in existing proposals. Specifically, the partial sum generation and addition are merged into a single carry-save addition operation. Also, module multipliers are replaced by simple adders by the bit unfolding and uncorrected residues technique. The CMAC reverse converters proposed here were fabricated in a 0.8 μm N-well CMOS process. Due to the techniques mentioned, the resulting VLSI implementation was 3-4 times smaller than recently reported results, while delivering identical throughput and achieving four times lower delay. The AT2 efficiency of these converters O(n2log3n) equals the best known to date. Comprehensive analysis of the various implementation options (CPA, CLA or serial) presented will be of great value to the VLSI system designer in choosing a reverse converter that conforms to the delay, area and power requirements imposed by a given application
LanguageEnglish
Pages229-235
Number of pages7
JournalIEE Proceedings - Computers and Digital Techniques
Volume145
Issue number3
StatusPublished - May 1998

Fingerprint

Converter
Binary
Adders
Reverse
Redundancy
Accumulate
Throughput
Multiplication
Partial Sums
Unfolding
Multiplier
Module
Requirements

Keywords

  • CMOS process
  • arithmetic codes
  • power requirements
  • residue number systems
  • VLSI
  • single carry-save addition operation
  • adders
  • addition
  • compressed multiply accumulate converters
  • partial sum generation
  • area
  • analogue-digital conversion
  • area-time-efficient VLSI residue-to-binary converters
  • delay
  • VLSI implementations

Cite this

Srikanthan, T., Bhardwaj, M., & Clarke, C. T. (1998). Area-time-efficient VLSI residue-to-binary converters.

Area-time-efficient VLSI residue-to-binary converters. / Srikanthan, T; Bhardwaj, M; Clarke, Christopher T.

In: IEE Proceedings - Computers and Digital Techniques, Vol. 145, No. 3, 05.1998, p. 229-235.

Research output: Contribution to journalArticle

Srikanthan, T, Bhardwaj, M & Clarke, CT 1998, 'Area-time-efficient VLSI residue-to-binary converters' IEE Proceedings - Computers and Digital Techniques, vol. 145, no. 3, pp. 229-235.
Srikanthan, T ; Bhardwaj, M ; Clarke, Christopher T. / Area-time-efficient VLSI residue-to-binary converters. In: IEE Proceedings - Computers and Digital Techniques. 1998 ; Vol. 145, No. 3. pp. 229-235
@article{fb40b626c4d54de5953b97894e1d4945,
title = "Area-time-efficient VLSI residue-to-binary converters",
abstract = "The authors present highly area-time-efficient VLSI implementations of residue reverse converters called compressed multiply accumulate (CMAC) converters. This efficiency results from carefully identifying and eliminating redundancy in existing proposals. Specifically, the partial sum generation and addition are merged into a single carry-save addition operation. Also, module multipliers are replaced by simple adders by the bit unfolding and uncorrected residues technique. The CMAC reverse converters proposed here were fabricated in a 0.8 μm N-well CMOS process. Due to the techniques mentioned, the resulting VLSI implementation was 3-4 times smaller than recently reported results, while delivering identical throughput and achieving four times lower delay. The AT2 efficiency of these converters O(n2log3n) equals the best known to date. Comprehensive analysis of the various implementation options (CPA, CLA or serial) presented will be of great value to the VLSI system designer in choosing a reverse converter that conforms to the delay, area and power requirements imposed by a given application",
keywords = "CMOS process, arithmetic codes, power requirements, residue number systems, VLSI, single carry-save addition operation, adders, addition, compressed multiply accumulate converters, partial sum generation, area, analogue-digital conversion, area-time-efficient VLSI residue-to-binary converters, delay, VLSI implementations",
author = "T Srikanthan and M Bhardwaj and Clarke, {Christopher T}",
year = "1998",
month = "5",
language = "English",
volume = "145",
pages = "229--235",
journal = "IEE Proceedings - Computers and Digital Techniques",
issn = "1350-2387",
publisher = "Institute of Electrical Engineers",
number = "3",

}

TY - JOUR

T1 - Area-time-efficient VLSI residue-to-binary converters

AU - Srikanthan,T

AU - Bhardwaj,M

AU - Clarke,Christopher T

PY - 1998/5

Y1 - 1998/5

N2 - The authors present highly area-time-efficient VLSI implementations of residue reverse converters called compressed multiply accumulate (CMAC) converters. This efficiency results from carefully identifying and eliminating redundancy in existing proposals. Specifically, the partial sum generation and addition are merged into a single carry-save addition operation. Also, module multipliers are replaced by simple adders by the bit unfolding and uncorrected residues technique. The CMAC reverse converters proposed here were fabricated in a 0.8 μm N-well CMOS process. Due to the techniques mentioned, the resulting VLSI implementation was 3-4 times smaller than recently reported results, while delivering identical throughput and achieving four times lower delay. The AT2 efficiency of these converters O(n2log3n) equals the best known to date. Comprehensive analysis of the various implementation options (CPA, CLA or serial) presented will be of great value to the VLSI system designer in choosing a reverse converter that conforms to the delay, area and power requirements imposed by a given application

AB - The authors present highly area-time-efficient VLSI implementations of residue reverse converters called compressed multiply accumulate (CMAC) converters. This efficiency results from carefully identifying and eliminating redundancy in existing proposals. Specifically, the partial sum generation and addition are merged into a single carry-save addition operation. Also, module multipliers are replaced by simple adders by the bit unfolding and uncorrected residues technique. The CMAC reverse converters proposed here were fabricated in a 0.8 μm N-well CMOS process. Due to the techniques mentioned, the resulting VLSI implementation was 3-4 times smaller than recently reported results, while delivering identical throughput and achieving four times lower delay. The AT2 efficiency of these converters O(n2log3n) equals the best known to date. Comprehensive analysis of the various implementation options (CPA, CLA or serial) presented will be of great value to the VLSI system designer in choosing a reverse converter that conforms to the delay, area and power requirements imposed by a given application

KW - CMOS process

KW - arithmetic codes

KW - power requirements

KW - residue number systems

KW - VLSI

KW - single carry-save addition operation

KW - adders

KW - addition

KW - compressed multiply accumulate converters

KW - partial sum generation

KW - area

KW - analogue-digital conversion

KW - area-time-efficient VLSI residue-to-binary converters

KW - delay

KW - VLSI implementations

M3 - Article

VL - 145

SP - 229

EP - 235

JO - IEE Proceedings - Computers and Digital Techniques

T2 - IEE Proceedings - Computers and Digital Techniques

JF - IEE Proceedings - Computers and Digital Techniques

SN - 1350-2387

IS - 3

ER -