Analysis of sampling clock phase noise in homodyne FMCW radar systems

In many contemporary electronic systems, phase noise sets the bound on the achievable performance. Radar systems are no exception, with the actual radar signals carrying significant amounts of phase noise due to the high transmit frequencies. In coherent radars, some of the phase noise sidebands on the received signal are cancelled due to mixing in the receiver. The sampling clock used to sample the intermediate frequency (IF) signals also introduces phase noise/jitter. This paper focuses on the contribution of the sampling clock's phase noise to the overall phase noise in the sampled signal in coherent homodyne FMCW radar systems. We develop a model relating the phase noise in the sampled signal to the phase noise in the radar signals and the jitter in the sampling clock. We apply our analysis to example FMCW radar systems. The derived model can be used to work out the phase noise requirement on the sampling clock for a given phase noise level in radar signals.