Abstract
An efficient FPGA implementation of an irrational CIC filter for decimation in digital receivers is presented in this paper. The proposed approach employs dual-port RAMs prevailing in almost all recent FPGAs, favorably decreases the number of used slices and increases the operating frequency. The circuit has been implemented on a Xilinx Virtex-II Pro XC2VP50-6 and has been used in some digital demodulators successfully. The decimator can properly apply a wide range of decimation factors from 1 to some hundreds and can work in frequencies up to 150 MHz in the mentioned FPGA.
| Original language | English |
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| Title of host publication | Proceedings of 9th International Symposium on Signal Processing and its Applications (ISSPA), 2007 |
| DOIs | |
| Publication status | Published - 27 Jun 2008 |
| Event | 2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007 - Sharjah, UAE United Arab Emirates Duration: 12 Feb 2007 → 15 Feb 2007 |
Conference
| Conference | 2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007 |
|---|---|
| Country | UAE United Arab Emirates |
| City | Sharjah |
| Period | 12/02/07 → 15/02/07 |
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ASJC Scopus subject areas
- Signal Processing
Cite this
An FPGA-based irrational decimator for digital receivers. / Beygi, Amir; Mohammadi, Ali; Abrishamifar, Adib.
Proceedings of 9th International Symposium on Signal Processing and its Applications (ISSPA), 2007. 2008. 4555382.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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TY - GEN
T1 - An FPGA-based irrational decimator for digital receivers
AU - Beygi, Amir
AU - Mohammadi, Ali
AU - Abrishamifar, Adib
PY - 2008/6/27
Y1 - 2008/6/27
N2 - An efficient FPGA implementation of an irrational CIC filter for decimation in digital receivers is presented in this paper. The proposed approach employs dual-port RAMs prevailing in almost all recent FPGAs, favorably decreases the number of used slices and increases the operating frequency. The circuit has been implemented on a Xilinx Virtex-II Pro XC2VP50-6 and has been used in some digital demodulators successfully. The decimator can properly apply a wide range of decimation factors from 1 to some hundreds and can work in frequencies up to 150 MHz in the mentioned FPGA.
AB - An efficient FPGA implementation of an irrational CIC filter for decimation in digital receivers is presented in this paper. The proposed approach employs dual-port RAMs prevailing in almost all recent FPGAs, favorably decreases the number of used slices and increases the operating frequency. The circuit has been implemented on a Xilinx Virtex-II Pro XC2VP50-6 and has been used in some digital demodulators successfully. The decimator can properly apply a wide range of decimation factors from 1 to some hundreds and can work in frequencies up to 150 MHz in the mentioned FPGA.
UR - http://www.scopus.com/inward/record.url?scp=51549121438&partnerID=8YFLogxK
U2 - 10.1109/ISSPA.2007.4555382
DO - 10.1109/ISSPA.2007.4555382
M3 - Conference contribution
SN - 9781424407798
BT - Proceedings of 9th International Symposium on Signal Processing and its Applications (ISSPA), 2007
ER -