An FPGA-based irrational decimator for digital receivers

Amir Beygi, Ali Mohammadi, Adib Abrishamifar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

An efficient FPGA implementation of an irrational CIC filter for decimation in digital receivers is presented in this paper. The proposed approach employs dual-port RAMs prevailing in almost all recent FPGAs, favorably decreases the number of used slices and increases the operating frequency. The circuit has been implemented on a Xilinx Virtex-II Pro XC2VP50-6 and has been used in some digital demodulators successfully. The decimator can properly apply a wide range of decimation factors from 1 to some hundreds and can work in frequencies up to 150 MHz in the mentioned FPGA.

Original languageEnglish
Title of host publication Proceedings of 9th International Symposium on Signal Processing and its Applications (ISSPA), 2007
DOIs
Publication statusPublished - 27 Jun 2008
Event2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007 - Sharjah, UAE United Arab Emirates
Duration: 12 Feb 200715 Feb 2007

Conference

Conference2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007
CountryUAE United Arab Emirates
CitySharjah
Period12/02/0715/02/07

ASJC Scopus subject areas

  • Signal Processing

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  • Cite this

    Beygi, A., Mohammadi, A., & Abrishamifar, A. (2008). An FPGA-based irrational decimator for digital receivers. In Proceedings of 9th International Symposium on Signal Processing and its Applications (ISSPA), 2007 [4555382] https://doi.org/10.1109/ISSPA.2007.4555382