An FPGA-based irrational decimator for digital receivers

Amir Beygi; Ali Mohammadi; Adib Abrishamifar

doi:10.1109/ISSPA.2007.4555382

An FPGA-based irrational decimator for digital receivers

Amir Beygi, Ali Mohammadi, Adib Abrishamifar

Department of Electronic & Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (SciVal)

Abstract

An efficient FPGA implementation of an irrational CIC filter for decimation in digital receivers is presented in this paper. The proposed approach employs dual-port RAMs prevailing in almost all recent FPGAs, favorably decreases the number of used slices and increases the operating frequency. The circuit has been implemented on a Xilinx Virtex-II Pro XC2VP50-6 and has been used in some digital demodulators successfully. The decimator can properly apply a wide range of decimation factors from 1 to some hundreds and can work in frequencies up to 150 MHz in the mentioned FPGA.

Original language	English
Title of host publication	Proceedings of 9th International Symposium on Signal Processing and its Applications (ISSPA), 2007
DOIs	https://doi.org/10.1109/ISSPA.2007.4555382
Publication status	Published - 27 Jun 2008
Event	2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007 - Sharjah, UAE United Arab Emirates Duration: 12 Feb 2007 → 15 Feb 2007

Conference

Conference	2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007
Country/Territory	UAE United Arab Emirates
City	Sharjah
Period	12/02/07 → 15/02/07

ASJC Scopus subject areas

Signal Processing

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10.1109/ISSPA.2007.4555382

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Beygi, A, Mohammadi, A & Abrishamifar, A 2008, An FPGA-based irrational decimator for digital receivers. in Proceedings of 9th International Symposium on Signal Processing and its Applications (ISSPA), 2007., 4555382, 2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007, Sharjah, UAE United Arab Emirates, 12/02/07. https://doi.org/10.1109/ISSPA.2007.4555382

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N2 - An efficient FPGA implementation of an irrational CIC filter for decimation in digital receivers is presented in this paper. The proposed approach employs dual-port RAMs prevailing in almost all recent FPGAs, favorably decreases the number of used slices and increases the operating frequency. The circuit has been implemented on a Xilinx Virtex-II Pro XC2VP50-6 and has been used in some digital demodulators successfully. The decimator can properly apply a wide range of decimation factors from 1 to some hundreds and can work in frequencies up to 150 MHz in the mentioned FPGA.

AB - An efficient FPGA implementation of an irrational CIC filter for decimation in digital receivers is presented in this paper. The proposed approach employs dual-port RAMs prevailing in almost all recent FPGAs, favorably decreases the number of used slices and increases the operating frequency. The circuit has been implemented on a Xilinx Virtex-II Pro XC2VP50-6 and has been used in some digital demodulators successfully. The decimator can properly apply a wide range of decimation factors from 1 to some hundreds and can work in frequencies up to 150 MHz in the mentioned FPGA.

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M3 - Conference contribution

AN - SCOPUS:51549121438

SN - 9781424407798

BT - Proceedings of 9th International Symposium on Signal Processing and its Applications (ISSPA), 2007

T2 - 2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007

Y2 - 12 February 2007 through 15 February 2007

ER -

An FPGA-based irrational decimator for digital receivers

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