The effect of optimising the transistor finger width on the performance of high-speed analogue circuits in deep sub-micron processes is investigated, demonstrated in a 28 nm high-K/metal gate CMOS technology process. Silicon proven results demonstrate that the oscillator with a finger width of 440 nm gives the best performance based on the figure of merit (=142) among the benchmark design examples used.
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Meng, F., Li, K., Thomson, D., Wilson, P., & Reed, G. T. (2018). Advanced layout techniques for high-speed analogue circuits in 28 nm HKMG CMOS process. Electronics Letters, 54(8), 486-488. https://doi.org/10.1049/el.2017.4453