Advanced layout techniques for high-speed analogue circuits in 28 nm HKMG CMOS process

Fan Meng, Ke Li, David Thomson, Peter Wilson, Graham T. Reed

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

The effect of optimising the transistor finger width on the performance of high-speed analogue circuits in deep sub-micron processes is investigated, demonstrated in a 28 nm high-K/metal gate CMOS technology process. Silicon proven results demonstrate that the oscillator with a finger width of 440 nm gives the best performance based on the figure of merit (=142) among the benchmark design examples used.
Original languageEnglish
Pages (from-to)486-488
Number of pages3
JournalElectronics Letters
Volume54
Issue number8
Early online date8 Mar 2018
DOIs
Publication statusPublished - 19 Apr 2018

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Analog circuits
Transistors
Silicon
Metals

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Advanced layout techniques for high-speed analogue circuits in 28 nm HKMG CMOS process. / Meng, Fan; Li, Ke; Thomson, David; Wilson, Peter; Reed, Graham T.

In: Electronics Letters, Vol. 54, No. 8, 19.04.2018, p. 486-488.

Research output: Contribution to journalArticle

Meng, Fan ; Li, Ke ; Thomson, David ; Wilson, Peter ; Reed, Graham T. / Advanced layout techniques for high-speed analogue circuits in 28 nm HKMG CMOS process. In: Electronics Letters. 2018 ; Vol. 54, No. 8. pp. 486-488.
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