The use of the Advanced Encryption Standard (AES) has become pervasive in a large number of communication applications. The hardware to implement AES is non trivial and as a result it has a significant overhead in its raw form. Despite the algorithm being inherently secure, side channel attacks have exposed potential weaknesses via the implementation route, particularly power analysis. As a result, much effort has been expended in identifying techniques to mask the power signature that can give away the secret key. Unfortunately, the hardware overhead is usually a significant proportion of the size of the original algorithm and in addition, the key can sometimes still be ascertained due to manufacturing differences (such as track lengths) still delivering aspects of the key in a power signature. This paper describes an approach that requires a simple modification to the implementation of the AES algorithm, without altering its basic characteristics, which provides a significantly improved strength against side channel attacks with a minimal additional hardware overhead.

Original languageEnglish
Title of host publication2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Number of pages4
Publication statusPublished - 2008
Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, USA United States
Duration: 18 May 200821 May 2008

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310


Conference2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Country/TerritoryUSA United States
CitySeattle, WA


  • AES
  • Countermeasure
  • DPA

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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