Achieving hardware-efficient neural network based pattern recognition system through linear approximation

SK Lam, T Srikanthan, CT Clarke, HS Low

Research output: Contribution to conferencePaper

Abstract

The limitations of traditional computers and the advent of real-time applications dictate the need for a dedicated hardware to realize complex neural network models that are widely used in pattern recognition systems. It has been shown that the computational bottleneck of the neural network architecture lies in the activation function. In this paper, we present an area-time efficient neural network engine that employs linear approximation to reduce the computational complexity of the activation function. It is demonstrated that the approximation method can achieve a high degree of recognition accuracy by trading-off the number of recognizable patterns. Hardware implementation results show that the proposed method has approximately 42% performance gain over the previous implementation with a hardware reduction of 123K NAND gates. The approach in this paper lends well for low-cost and high-speed portable applications such as intelligent toys.
Original languageEnglish
DOIs
Publication statusPublished - Nov 2004
Event38th Asilomar Conference on Signals, Systems and Computers - California, USA United States
Duration: 7 Nov 200410 Nov 2004

Conference

Conference38th Asilomar Conference on Signals, Systems and Computers
CountryUSA United States
CityCalifornia
Period7/11/0410/11/04

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