A reconfigurable architecture for real-time digital simulation of neurons

Peter Wilson; Benjamin Metcalfe; Jonathan Graham-Harper-Cater; Julian A. Bailey

doi:10.1109/IntelliSys.2017.8324340

A reconfigurable architecture for real-time digital simulation of neurons

Peter Wilson, Benjamin Metcalfe, Jonathan Graham-Harper-Cater, Julian A. Bailey

Research output: Chapter or section in a book/report/conference proceeding › Chapter in a published conference proceeding

2 Citations (SciVal)

Abstract

A major problem in computational neuroscience is the large scale biologically realistic neuron simulations which require massive amount of computing resources, which in turn requires large amount of power. This poses a significant problem when we look towards a potential future where machines have 'silicon brains'. In this paper we build on previous VHDL neuron work by building a programmable neuron device housing 116 neurons and 200 synapses to perform realistic, real-time simulations of neuron networks in hardware. This flexible architecture is loaded with the C. Elegans locomotion system that demonstrates that the behavior of the programmable architecture is the same as the behavior of the design from previous work.

Original language	English
Title of host publication	2017 Intelligent Systems Conference, IntelliSys 2017
Publisher	IEEE
Pages	66-75
Number of pages	10
Volume	2018-January
ISBN (Electronic)	9781509064359
DOIs	https://doi.org/10.1109/IntelliSys.2017.8324340
Publication status	Published - 23 Mar 2018
Event	2017 Intelligent Systems Conference, IntelliSys 2017 - London, UK United Kingdom Duration: 7 Sept 2017 → 8 Sept 2017

Conference

Conference	2017 Intelligent Systems Conference, IntelliSys 2017
Country/Territory	UK United Kingdom
City	London
Period	7/09/17 → 8/09/17

Keywords

hardware
network
Neuron
programmable
simulation

ASJC Scopus subject areas

Computer Science Applications
Computer Networks and Communications
Artificial Intelligence
Computer Vision and Pattern Recognition
Control and Optimization

Access to Document

10.1109/IntelliSys.2017.8324340

Cite this

Wilson, P , Metcalfe, B , Graham-Harper-Cater, J & Bailey, JA 2018, A reconfigurable architecture for real-time digital simulation of neurons. in 2017 Intelligent Systems Conference, IntelliSys 2017. vol. 2018-January, IEEE, pp. 66-75, 2017 Intelligent Systems Conference, IntelliSys 2017, London, UK United Kingdom, 7/09/17. https://doi.org/10.1109/IntelliSys.2017.8324340

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abstract = "A major problem in computational neuroscience is the large scale biologically realistic neuron simulations which require massive amount of computing resources, which in turn requires large amount of power. This poses a significant problem when we look towards a potential future where machines have 'silicon brains'. In this paper we build on previous VHDL neuron work by building a programmable neuron device housing 116 neurons and 200 synapses to perform realistic, real-time simulations of neuron networks in hardware. This flexible architecture is loaded with the C. Elegans locomotion system that demonstrates that the behavior of the programmable architecture is the same as the behavior of the design from previous work.",

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AB - A major problem in computational neuroscience is the large scale biologically realistic neuron simulations which require massive amount of computing resources, which in turn requires large amount of power. This poses a significant problem when we look towards a potential future where machines have 'silicon brains'. In this paper we build on previous VHDL neuron work by building a programmable neuron device housing 116 neurons and 200 synapses to perform realistic, real-time simulations of neuron networks in hardware. This flexible architecture is loaded with the C. Elegans locomotion system that demonstrates that the behavior of the programmable architecture is the same as the behavior of the design from previous work.

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A reconfigurable architecture for real-time digital simulation of neurons

Abstract

Conference

Keywords

ASJC Scopus subject areas

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