This paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2nd order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35μm BSim3v3 CMOS models of two PLL designs (10MHz FSK demodulator, 500MHz frequency synthesizer) are included.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 2005|
|Event||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan|
Duration: 23 May 2005 → 26 May 2005
ASJC Scopus subject areas
- Electrical and Electronic Engineering