A novel switched-current phase locked loop

Reuben Wilcock; Peter Wilson; Bashir M. Al-Hashimi

doi:10.1109/ISCAS.2005.1465212

A novel switched-current phase locked loop

Reuben Wilcock, Peter Wilson, Bashir M. Al-Hashimi

University of Southampton

Research output: Contribution to journal › Conference article › peer-review

3 Citations (SciVal)

Abstract

This paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2^nd order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35μm BSim3v3 CMOS models of two PLL designs (10MHz FSK demodulator, 500MHz frequency synthesizer) are included.

Original language	English
Article number	1465212
Pages (from-to)	2815-2818
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1465212
Publication status	Published - 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 23 May 2005 → 26 May 2005

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/ISCAS.2005.1465212

Cite this

@article{bb208b7258a84b2ba0db47298e1d67e9,

title = "A novel switched-current phase locked loop",

abstract = "This paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2nd order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35μm BSim3v3 CMOS models of two PLL designs (10MHz FSK demodulator, 500MHz frequency synthesizer) are included.",

author = "Reuben Wilcock and Peter Wilson and Al-Hashimi, {Bashir M.}",

year = "2005",

doi = "10.1109/ISCAS.2005.1465212",

language = "English",

pages = "2815--2818",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "IEEE",

note = "IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 ; Conference date: 23-05-2005 Through 26-05-2005",

}

TY - JOUR

T1 - A novel switched-current phase locked loop

AU - Wilcock, Reuben

AU - Wilson, Peter

AU - Al-Hashimi, Bashir M.

PY - 2005

Y1 - 2005

N2 - This paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2nd order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35μm BSim3v3 CMOS models of two PLL designs (10MHz FSK demodulator, 500MHz frequency synthesizer) are included.

AB - This paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2nd order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35μm BSim3v3 CMOS models of two PLL designs (10MHz FSK demodulator, 500MHz frequency synthesizer) are included.

UR - http://www.scopus.com/inward/record.url?scp=54949151437&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2005.1465212

DO - 10.1109/ISCAS.2005.1465212

M3 - Conference article

AN - SCOPUS:54949151437

SN - 0271-4310

SP - 2815

EP - 2818

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 1465212

T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

Y2 - 23 May 2005 through 26 May 2005

ER -

A novel switched-current phase locked loop

Abstract

ASJC Scopus subject areas

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