A novel switch-current phase locked loop

Reuben Wilcock; Peter R. Wilson; Bashir Al-Hashimi

A novel switch-current phase locked loop

Reuben Wilcock, Peter R. Wilson, Bashir Al-Hashimi

Department of Electronic & Electrical Engineering

Research output: Contribution to conference › Paper

Abstract

This paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2nd order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35?m BSim3v3 CMOS models of two PLL designs (10MHz FSK demodulator, 500MHz frequency synthesizer) are included.

Original language	English
Publication status	Published - 2005
Event	IEEE International Symposium on Circuits and Systems (ISCAS 2005) - Kobe, Japan Duration: 23 May 2005 → 26 May 2005

Conference

Conference	IEEE International Symposium on Circuits and Systems (ISCAS 2005)
Country/Territory	Japan
City	Kobe
Period	23/05/05 → 26/05/05

Cite this

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title = "A novel switch-current phase locked loop",

abstract = "This paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2nd order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35?m BSim3v3 CMOS models of two PLL designs (10MHz FSK demodulator, 500MHz frequency synthesizer) are included.",

author = "Reuben Wilcock and Wilson, {Peter R.} and Bashir Al-Hashimi",

year = "2005",

language = "English",

note = "IEEE International Symposium on Circuits and Systems (ISCAS 2005) ; Conference date: 23-05-2005 Through 26-05-2005",

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TY - CONF

T1 - A novel switch-current phase locked loop

AU - Wilcock, Reuben

AU - Wilson, Peter R.

AU - Al-Hashimi, Bashir

PY - 2005

Y1 - 2005

N2 - This paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2nd order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35?m BSim3v3 CMOS models of two PLL designs (10MHz FSK demodulator, 500MHz frequency synthesizer) are included.

AB - This paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2nd order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35?m BSim3v3 CMOS models of two PLL designs (10MHz FSK demodulator, 500MHz frequency synthesizer) are included.

UR - http://eprints.soton.ac.uk/260404/

M3 - Paper

T2 - IEEE International Symposium on Circuits and Systems (ISCAS 2005)

Y2 - 23 May 2005 through 26 May 2005

ER -

A novel switch-current phase locked loop

Abstract

Conference

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