A novel switch-current phase locked loop

Reuben Wilcock, Peter R. Wilson, Bashir Al-Hashimi

Research output: Contribution to conferencePaper

Abstract

This paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2nd order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35?m BSim3v3 CMOS models of two PLL designs (10MHz FSK demodulator, 500MHz frequency synthesizer) are included.
Original languageEnglish
Publication statusPublished - 2005
EventIEEE International Symposium on Circuits and Systems (ISCAS 2005) - Kobe, Japan
Duration: 23 May 200526 May 2005

Conference

ConferenceIEEE International Symposium on Circuits and Systems (ISCAS 2005)
CountryJapan
CityKobe
Period23/05/0526/05/05

Fingerprint

Phase locked loops
Switches
Frequency synthesizers
Frequency shift keying
Demodulators
Detectors
Networks (circuits)

Cite this

Wilcock, R., Wilson, P. R., & Al-Hashimi, B. (2005). A novel switch-current phase locked loop. Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan.

A novel switch-current phase locked loop. / Wilcock, Reuben; Wilson, Peter R.; Al-Hashimi, Bashir.

2005. Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan.

Research output: Contribution to conferencePaper

Wilcock, R, Wilson, PR & Al-Hashimi, B 2005, 'A novel switch-current phase locked loop', Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan, 23/05/05 - 26/05/05.
Wilcock R, Wilson PR, Al-Hashimi B. A novel switch-current phase locked loop. 2005. Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan.
Wilcock, Reuben ; Wilson, Peter R. ; Al-Hashimi, Bashir. / A novel switch-current phase locked loop. Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan.
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abstract = "This paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2nd order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35?m BSim3v3 CMOS models of two PLL designs (10MHz FSK demodulator, 500MHz frequency synthesizer) are included.",
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AB - This paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2nd order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35?m BSim3v3 CMOS models of two PLL designs (10MHz FSK demodulator, 500MHz frequency synthesizer) are included.

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